Abstract: A DBS receiver front end which converts the received signal directly to the baseband representation and maintains a high performance with a new techniques for tracking and counteracting frequency drift, and correcting I/Q angular error and amplitude imbalance. The DBS receiver front end comprises a tuner and a demodulator/decoder. The tuner receives a high frequency signal and converts it to a baseband signal having a frequency offset error. In one embodiment, the DBS receiver front end includes a demodulator/decoder which digitally performs I/Q angular error correction. The tuner converts the high frequency signal to a baseband signal having an in-phase and a quadrature-phase component. Ideally, the components are separated by ninety degrees, but typically an angular error exists. The demodulator/decoder includes an adaptive equalizer for correcting the angular error. Having the equalizer allows for relaxed tolerances in the tuner.

Abstract: A system for computing an affinity for relocating a cell on a surface of a semiconductor chip is disclosed herein. The cell is located within a region and belongs to a net of cells. The system initially computes a weight associated with all cells in the net. The sytem then sums the weights of all cells in the net containing the cell for all cells located inside the region and at positions greater than and less than edges of the region and computes the affinity for moving the cell to points on the surface greater than, equal to, and less than the current position of the cell based on the weight sums from said summing function. The computing function further comprises combining the affinities determined based on weight sums with other affinities. The summing function further comprises computing a relationship between the amount of rows and columns of regions on the semiconductor chip surface, and the affinity computation function comprises combining the relationship with the weight sums.

Abstract: Methods and systems of automatically generating synthesis scripts and hierarchical flow/connectivity diagrams are provided. The user inputs design constraints, clock characteristics, technology files, and HDL code. The system handles cores, megafunctions, hardmacs, and black boxes appropriately for synthesis. During synthesis, individual modules in the HDL code may change. The system manages these incremental changes by generating incremental scripts which 1) compile, map and model the modules that have been changed and 2) characterize, compile and model the modules that have been changed in the hierarchy under that instance. During the iterative design process, new hierarchical flow diagrams may be generated to understand the full effect of the incremental changes.

Abstract: A programmable, byte wise, multimedia bitstream parser comprises an input data organizer, a data management buffer, a register file, a logical unit and a microprogram controller. A data source alternatively provides a bitstream to a parallel or serial port and the input data organizer, which includes a serial to parallel converter and a multiplexer, arranges the incoming data into a parallel stream of bytes for passage to the data management buffer. Status flags are associated with each byte passing through the management buffer to facilitate data processing, including start code and context identification and error handling. The register file includes counters and intermediate data buffers for processing a plurality of layers with data quantities which are not predetermined by syntax. Additionally, the register file is provided in tandem for dual context processing.

Abstract: A circuit for holding constant the propagation delay time at an output terminal in response to an input signal having a varying transition time from one logic state to another logic state at an input terminal is provided. The circuit has a plurality of inverters, each inverter having an input node and an output node, connected in series between the input terminal and the output terminal. The circuit also has a first capacitive means coupled to one of the first inverter output nodes through a switch, and has a means coupled between the input terminal and the switch for engaging the switch to couple the capacitive means to one of the first inverter output nodes. The engaging means is timed to couple the capacitive means responsive to the transition time of the input signal whereby the propagation delay time at the output terminal is constant.

Abstract: A communications receiver system is presented for detecting burst errors and providing erasure information to the block decoder, thereby effectively doubling the conventional correction capability of the block decoder with only a minimal increase in complexity. In one embodiment, this mechanism takes the form of a circuit which re-encodes the output of the inner decoder, compares it with the received sequence of code symbols, and flags a portion of the inner decoder output for erasure when an excessive number of code symbol errors are detected. In a second embodiment, this mechanism takes the form of a circuit which makes hard symbol decisions on the channel signal, compares the hard decisions to the channel signal to determine a noise level, and thereafter flags the channel output in regions with excessive noise levels.

Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.

Abstract: A memory circuit which enables storage of more than two logic states in a memory cell. Since the additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit. The disclosed memory circuit comprises an analog-to-digital converter coupled to detect a current through a transistor in a memory cell. The current is determined by a charge stored on the transistor's gate. By enabling the current to be detected in discrete increments, it becomes possible to represent more than one bit of information with the charge stored in the memory cell. Usage of additional increments necessitates more precise storage and detection circuitry. In one embodiment, the storage circuitry uses feedback to obtain a greater logic state retrieval accuracy.

Abstract: A method of making, including a method of floorplanning, an integrated circuit includes the separation of electrical logic function cells of the integrated circuit into sets or macros of data path cells, each of which evidence a high level of similarity or repetitiveness in the integrated circuit, and into sets of random logic cells, which each are connected to data path cells but which do not meet topological and connectivity criteria for the data path cells. The data path cells are iteratively sorted according to connectivity requirements and are initially placed on a provisional floor plan of the integrated circuit in a cell-space matrix of rows and columns, the rows being of substantially uniform width to accommodate functional modules of the data path cells, and the rows being of variably height to cooperatively define the spaces of the cell-space matrix.

Abstract: A system for optimizing placement of a plurality of cells located on a surface of a semiconductor chip divided into regions by grid lines is disclosed herein. The system first increases the size associated with each cell by a fixed amount. The system then performs various density equalization routines to all cells, and locates cells having a size greater than a predetermined quantity and fixes those cells. Finally, the system executes a plurality of optimal cell movement routines to crystallize cell placement.

Abstract: A semiconductor memory layout definition for connection to a power supply bus in an integrated circuit layout pattern. The layout definition includes an outline and a plurality of power supply conductor segments within the outline. At least one of the power supply conductor segments has a direct strap identifier which indicates a desired attachment to the power supply bus. The direct strap identifier is passed to a routing design tool which routes a direct strap conductor from the power supply bus to the power supply conductor segments having the direct strap identifier.

Abstract: A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a "tri-ister" is disclosed.

Abstract: A socket for testing an integrated circuit ball grid array package having external contacts formed by an array of solder balls is formed with a flexible bladder in the socket bottom. The upper side of the bladder has a test contact pattern that matches the pattern of the solder balls on the package. The side of the bladder carrying the test contact pattern is formed of conventional flexible circuit tape having contacts of spherical, conical or cylindrical shape formed thereon by conventional techniques, with circuit traces also formed on the flexible circuit tape extending to the outside of the socket for connection to test circuitry. Inflation of the bladder drives its test contact pattern against the solder balls of a package held in the socket and forces the flexible test contact substrate of the bladder to conform to any non-planar configuration of the ball grid array.

Abstract: A process of forming a tungsten contact plug, on an integrated circuit (IC), that is substantially free of seam formation is described. The process includes forming a dielectric layer on a surface of a substrate, forming a via in the dielectric layer, blanket depositing a first bulk layer of tungsten on the dielectric layer and partially filling the via, blanket depositing an amorphous or a microcrystalline layer of tungsten over the first bulk layer of tungsten such that growth of tungsten grains inside the via is effectively inhibited, and blanket depositing a second bulk layer of tungsten on the amorphous or microcrystalline layer.

Abstract: A method of inspecting a photomask for use in photolithography which accounts for the rounding of corners of features that occurs during manufacture of the photomask. A data tape used in the preparation of the photomask is first provided. An inspection tape is then prepared by modifying the data on the data tape to account for rounding of the features during preparation of the photomask. Finally, an inspection device is used to compare features on the photomask to data on the inspection tape corresponding to such features.

Abstract: A time-division data multiplexer has feedback for adjusting the select clock cross-over voltage. The multiplexer includes a multi-phase clock generator having a plurality of select clock outputs with different phases, a plurality of parallel data inputs and first and second serial data outputs. A first set of gating transistors is coupled between the first data output and a common node. Each transistor in the first set is gated by a corresponding data input and at least one corresponding select clock output. A second set of gating transistors is coupled between the second data output and the common node. Each transistor in the second set is gated by a corresponding data input and at least one corresponding select clock output. A first current source is coupled to the common node.

Abstract: Electronic systems using separate and distinct conductive layers for power and ground are insulated from one another and a patterned signal conductive layer to form a flexible substrate for mounting a semiconductor die in a semiconductor device assembly of the system. TAB technology is utilized to produce an assembly that has superior electrical characteristics because power and ground is conducted on separate low impedance conductive layers. The power and ground leads connecting the semiconductor die and external circuits are selected from the signal trace layer, cut bent downward and attached by bonding to the respective power or ground layer. A tool is disclosed for cutting the selected leads. The present invention further provides a system utilizing a wafer probe card which includes a multi-layer, relatively flexible tape-like substrate having a first conductive layer patterned to have a number of probe leads thereon.

Abstract: A method of assembling flip chips in a package. Solder bumps are attached to a first flip chip and to a second flip chip. A package substrate having first and second opposing sides is provided, and the first flip chip is electrically connected to the first side of the package substrate using the solder bumps attached to the first flip chip. The second flip chip is also electrically connected to the second side of the package substrate using the solder bumps attached to the second flip chip. The position of the second flip chip is substantially opposed to and aligned with the position of the first flip chip. The first and second flip chips are under filled with a heat conductive epoxy. The first flip chip is encapsulated against the first side of the package substrate, and the second flip chip is encapsulated against the second side of the package substrate. Solder balls are attached to the first side of the package insert.

Abstract: An asynchronous transfer mode (ATM) processing system interconnection or termination unit is implemented on a single integrated circuit chip. The unit includes a universal protocol device having Virtual Channel Memory (VCR) for storing ATM cells for segmentation and reassembly, a Direct Memory Access (DMA) controller for interconnecting the VCR to a host unit, and a Parallel Cell Interface (PCI) for interconnecting the VCR to an ATM network. A Reduced Instruction Set Computer (RISC) microprocessor controls the DMA controller as well as segmentation and reassembly of Conversion Sublayer Payload Data Unit (CS-PDU)s and transfer between the memory, the host and the ATM network and other operations of the device using single clock cycle instructions. The operating program for the RISC microprocessor is stored in a volatile Instruction Random Access Memory (IRAM) in the form of firmware which is downloaded at initialization.

Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.