Abstract: A microelectronic integrated circuit includes a semiconductor substrate, and a plurality of microelectronic devices formed on the substrate. Each device has a periphery defined by a hexagon, and includes an active area formed within the periphery, a central terminal formed in a central portion of the active area, and interconnected first to third terminals formed in the active area adjacent to edges of the hexagon that are separated by other edges. First to third gates are formed between the first to third terminals respectively and the central terminal, and have contacts formed outside the active area adjacent to the other edges of the hexagon. The power supply connections to the central terminal and the first to third terminals, the conductivity type (NMOS or PMOS), and the addition of a pull-up or a pull-down resistor is selected for each device to provide a desired OR, NOR, AND or NAND function. The devices are interconnected using three direction routing based on hexagonal geometry.

Abstract: A driver circuit has a single feedback transistor in the driver transistor well to provide a momentary feedback from source to gate and maintain conductance of the driver transistor during turnoff of the driver transistor and thus reduce ringing oscillation at the transistor source output. An enable/disable signal is applied to control conduction circuitry and the driver transistor and force the output to a high impedance state when the circuit is disabled. Clocked operation of the driver circuit is provided with circuitry merged with a latch. A terminal for receiving a global i.sub.dd test signal controls circuitry removing power to the driver circuit and applying a ground potential to the driver output in response to the global i.sub.dd test signal.

Abstract: A laser is used to cut or "zap" unwanted sections of an aluminum interconnect metallization pattern on a microelectronic circuit substrate. Vaporized aluminum forms a cloud above the substrate that is reacted with a gas to form a substance which can be prevented from solidifying and forming a conductive residue on the substrate that could create a short circuit in the metallization pattern. The gas can be pressurized oxygen, in which case the reactant substance is electrically insulative aluminum oxide that forms a desirable sealing coating over the cut area. The aluminum oxide has a lower density than aluminum, and expands in the cut area to form a hermetic seal with the facing edges of the metallization pattern. Alternatively, the gas can be chlorine or other material which forms a residue that can be easily removed using a solvent such as water.

Abstract: A CMOS integrate circuit has improved protection to damage from electrostatic discharge (ESD) events because the circuit is formed with a virtual lateral bipolar transistor submerged in the morphology of the integrated circuit beneath an active circuit element of the circuit, and being formed by impurity atoms implanted into the substrate structure as ions which disperse laterally to form a dispersed charge permeation zone through which surge current from an ESD is conducted safely at a current level sufficiently low that the substrate material of the integrated circuit is not damaged. The integrated circuit may be formed with an intrinsic zener diode having a reverse bias breakdown voltage high enough to not interfere with the normal operation of the integrated circuit, and low enough to allow surge current from an ESD event to safely flow to ground potential.

Abstract: A system and method for detecting the voltage level of a power supply signal and generating a notification signal to indicate when the supply voltage exceeds a minimum voltage that is programmable by a user. A programming signal, that allows for multiple voltages to be detected, is applied to the voltage detection system to generate a notification signal in response to the supply voltage attaining the minimum voltage indicated by the programming signal.

Abstract: For physical protection and to reduce stress, an electronic device (10) is mounted within a cavity in a housing (14) which constitutes an encapsulating member. The housing is preferably formed as two premoulded piece parts (14a, 14b). A leadframe (12) extends into the housing (14) in the manner of a sandwich construction. The device (10) may be mounted on a heat sink (16).

Abstract: Techniques for providing semiconductor packages capable of forming connections to "high I/O" semiconductor dies is described, wherein there are at least two distinct pluralities of conductive lines. Leadframe-type packages and substrate-based package embodiments are described.

Abstract: Via filling is enhanced by the techniques of 1) providing pillars immediately underneath semiconductor features, such as metal layer contacts (inter-connection points), and 2) polishing off excess via-filling material so that the via-filling plug is flush with the topmost insulating layer. The pillars are provided under every feature over which a via will be formed, so that an insulating layer surrounding the via will be thinner at the location of the feature. If necessary, polishing is continued to thin the insulating layer so that the plugs in initially selectively under-filled vias are made flush with the insulating layer. Method and apparatus are disclosed.

Abstract: A technique for integrated circuit floorplanning using irregularly shaped dies (e.g., triangular, elongated rectangular, parallelogram-shaped, etc.) is described whereby the layout of the integrated circuit die is accomplished by partitioning (slicing) the die into progressively smaller groups of more than two areas into which functions (active elements, or circuits) are assigned according to their area requirements. The die is iteratively sub-partitioned.

Abstract: A method and structure for wafer level testing of integrated circuit dice. A plurality of conductive paths are formed from a sacrificial metal layer and routed through the scribing lanes of the wafer. These conductive paths extend from selected I/O pads of the integrated circuit dice to an other portion of the wafer. Multiplexing and testing circuitry may also be formed on the wafer to facilitate integrated circuit testing. The novel method of the present invention further includes the step of removing the conductive paths before the wafer is segmented or otherwise operationally used. In one embodiment the conductive paths are formed from a conductive material differing from the conductive material used to form the I/O pads of the integrated circuits. Etching or heating may then preferentially remove the conductive paths prior to segmenting or otherwise operationally using the wafer.

Abstract: Methods of etching optical elements in association with photosensitive elements are described. In some of the arrangements, the optical elements are formed integrally with a substrate containing the photosensitive elements. In other arrangements, an optical element is mounted to a package, or the like, containing the substrate and photosensitive elements. In other arrangements, two or more optical elements are employed, including conventional refractive elements, refractive focusing elements, and refractive beam splitting elements. Utility as solid state image sensors is discussed. Utility for monochromatic and color imaging is discussed.

Abstract: The present invention provides a method for fabricating an integrated circuit package, as well the resulting integrated circuit package, which retains a heatsink in close communication with a mold cavity. This precludes any encapsulant from flowing between the heatsink and the inner surface of a mold cavity. As a consequence, the bottom of the heatsink is not encapsulated and is thus exposed. This is accomplished by including posts, attached to the leadframe assembly, which have the function of exerting a downward force on a leadframe assembly and, in turn, on the heatsink. Tie bars, which are non-functional parts of a leadframe assembly, can be utilized as posts by bending the posts into an upright position.

Abstract: A low cost and easily implemented apparatus and method for synchronizing serially connected clock circuits is ideally suited to audio applications. The circuit takes data from a bitstream clock source and from the local source and counts the number of pulses received from each. A desired clock count is calculated based as a multiple of the ratio of the bitstream clock source frequency to the local clock signal frequency. Based on the samples received from the bitstream clock relative to the local clock at a late point in time, samples are either repeated or dropped to correct any error in the bitstream signal.

Abstract: An Electronic Computer Aided Design System provides for concurrent operation of a plurality of design tools which share a common design dataset. Changes made by one program to the design dataset are immediately updated and are automatically reflected in the displayed outputs of the other design tools. A tool manager program allows rule-based automation of the entire system.

Abstract: A methodology for generating structural descriptions of complex digital devices from high-level descriptions and specifications is disclosed. The methodology uses a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is essentially a series of transformations operating upon various levels of design representations. At each level, the intended meaning (semantics) and formal software manipulations are captured to derive a more detailed level describing hardware meeting the design goals. Important features of the methodology are: capturing the users concepts, intent, specification, descriptions, constraints and trade-offs; architectural partitioning; what-if analysis at a high level; sizing estimation; timing estimation; architectural trade-off; conceptual design with implementation estimation; and timing closure.

Abstract: A method for manufacturing an ohmic contact on a semiconductor device, as disclosed herein, includes a first step of etching a via through a non-conductive layer formed over a partially fabricated version of the semiconductor device. This step exposes a region of a device element such as a source, gate electrode, etc. Next, an ohmic contact layer including tantalum and silicon is deposited over the partially fabricated device and in the vias by sputtering in an argon atmosphere. Thereafter, and in the same processing apparatus, a barrier layer including a tantalum silicon nitride is deposited over the ohmic contact layer. Then an aluminum alloy metallization layer is directly deposited on the partially fabricated device at a temperature of at least 650.degree. C. At this deposition temperature, the metallization layer conformally fills the via, thereby producing a stable, uniform contact.

Abstract: A compact MOS type active device is constructed at least partially in an opening in an insulation layer, such as an oxide layer, above a portion of a semiconductor substrate forming a first source/drain region of the MOS type active device. A semiconductor material, on the sidewall of the opening, and in electrical communication with the portion of the substrate forming the first source/drain region of the device, comprises the channel portion of the MOS device. A second source/drain region, in communication with an opposite end of the channel, is formed on the insulation layer adjacent the opening and in electrical communication with the channel material in the opening. A gate oxide layer is formed over the channel portion and at least partially in the opening, and a conductive gate electrode is then formed above the gate oxide.

Abstract: A method and apparatus for testing semiconductor devices at device operating speed for both proper combinational and timing logic functions with a standard low speed logic tester. A high speed phase-lock-loop system clock of the semiconductor device is frequency and phase locked to the lower speed logic tester clock. Test data is shifted into the semiconductor device at the test clock speed. Two controlled system clock pulses are utilized to clock the test data into the semiconductor devices. The first of these two pulses starts the test and the second ends the test. In this way, the combinational functions of the semiconductor devices are tested at the system operating speed.

Abstract: A packaged semiconductor device, leadframe for making same, and method of mounting same to a printed circuit board are described. The device has a body, and a plurality of leads extending from the body. One or more alignment features are formed on the exterior of the package body, for maintaining precise alignment of the device with respect to a printed wiring board. The alignment feature is a tab formed as part of portion of the leadframe external to the package body. The tab may have various shapes, and may be provided with a hole for registering with a pin on an underlying substrate, such as a printed wiring board. The pin and the tab may be electrically connected.

Abstract: A conductive member is described with a surface of controlled roughness thereon which is useful in the construction of an integrated circuit structure. In a preferred embodiment, the conductive member is formed using a mixture of germanium and silicon which is then oxidized, resulting in the formation of a roughened surface on the germanium/silicon conductive member due to the difference in the respective rates of oxidation of the germanium and silicon. After oxidation of the conductive member, the oxide layer may be removed, leaving the roughened surface on the germanium/silicon conductive member. When an integrated circuit structure such as an EPROM is to be formed using this conductive member with a roughened surface, a further layer of oxide is then deposited over the roughened surface followed by deposition of a second layer of conductive material such as polysilicon or a germanium/silicon mixture, from which the control gate will be formed.