Abstract: Changing (varying, irregular) resist thickness on semiconductor wafers having irregular top surface topography or having different island sizes, affects the percent reflectance (and absorption efficiency) of incident photolithographic light, and consequently the critical dimensions of underlying features being formed (e.g., polysilicon gates). A low solvent content resist solution that can be applied as an aerosol provides a more uniform thickness resist film, eliminating or diminishing photoresist thickness variations. A top antireflective coating (TAR) also aids in uniformizing reflectance, despite resist thickness variations. The two techniques can be used alone, or together. Hence, better control over underlying gate size can be effected, without differential biasing.

Abstract: A Motion Picture Experts Group (MPEG) video/audio data bitstream includes macroblocks of video data which can each include input Motion Compensation (M) data and input discrete cosine Transform Coded (I) data. A motion pipeline processes the input M data to produce processed M data, and a transform pipeline processes the input I data to produce processed I data. A controller controls the motion pipeline and the transform pipeline to concurrently process the input M data and the input I data respectively such that a length of time required for processing each macroblock is variable and is determined by the largest of a length of time required for the motion pipeline to process the input M data and a length of time required for the transform pipeline to process the input I data of the macroblock.

Abstract: A self-timed memory control system including a dummy row and column of memory cells along adjacent edges of a core memory array. Control logic receives an external clock signal and initiates address decoding, and also asserts a sense enable signal for activating the sense amplifiers. A dummy driver receives the enable signal and asserts a select signal on a dummy select line, which causes a memory access to occur in the dummy portion simultaneously with each access of the core memory array. A fixed memory cell in the dummy path always asserts a logic zero to a dummy sense amplifier, which senses the logic zero and respondingly asserts a timing signal. The dummy sense amplifier is biased with a voltage offset to favor a logic one, so that the timing signal is preferably delayed until after the output data of the core memory array has stabilized.

Abstract: Various techniques for forming superconductive lines are described whereby superconductive lines can be formed by stamping, etching, polishing, or by rendering selected areas of a superconductive film (layer) non-superconductive. The superconductive material can be "perfected" (or optimized) after it is formed into lines (traces). In one embodiment, trenches are etched in a substrate, the trenches are filled with superconductive material, and any excess superconductive material overfilling the trenches is removed, such as by polishing. In another embodiment, superconductive lines are formed by rendering selected areas of a superconductive layer (i.e., areas other than the desired superconductive lines) non-superconductive by "damaging" the superconductive material by laser beam heating, or by ion implantation. Superconductive lines formed according to the invention can be used to protect semiconductor devices (e.g.

Abstract: A driver circuit formed from CMOS material is provided for receiving an input logic signal from an internal CMOS circuit and inducing a corresponding output signal onto a terminated transmission line. The driver circuit comprises a pre-driver inverter having an input and an output. The inverter inverts a logic state of the input logic signal. The driver circuit also includes an output transistor that provides the output signal and has a drain electrically connected to the transmission line. The driver circuit also includes a control circuit for controlling the output signal during a transition of the input logic signal from a first logic state to a second logic state. The driver circuit is physically isolated from the internal CMOS circuit.

Abstract: An integrated circuit structure with input/output gate voltage regulation and parasitic zener and junction diodes for protection against damage resulting from electrostatic discharge (ESD) events. The circuit includes a first protective FET connected between an input/output pad and a ground potential of the integrated circuit. A diode voltage regulator is also connected between the gate of the first protective FET and a reference potential of the integrated circuit. The first protective FET receives a voltage from its gate-drain overlap capacitance during an ESD event. The diode is operative during an ESD event to provide a sufficient voltage to the first FET gate to permit a desired ESD current flow through the first protective FET. In one embodiment the first FET is an NMOS device and the diode voltage regulator is a series of p-n forward biased diodes.

Abstract: A dambar-less leadframe is sandwiched between two printed circuit boards (PCBs). The PCBs form a major portion of the package body, and isolate the leadframe leads from plastic molding compound. In one embodiment, an upper PCB (substrate) is formed as a ring, having an opening containing a heat sink element. A lower PCB is also formed as a ring, and has a smaller opening for receiving a die. The back face of the die is mounted to the heat sink. The exposed front face of the die is wire bonded to inner ends of conductive traces on the exposed face of the lower PCB. The outer ends of the traces are electrically connected to the leadframe leads by plated-through vias extending through the two PCBs. The plated-through vias additionally secure the sandwich structure together. Plastic molding compound is injection/transfer molded over the front face of the die and the bond wires, forming a partially-molded package. In another embodiment, the upper PCB is a solid planar element.

Abstract: An apparatus and method implementing an algorithm for determining the most likely least recently used cache line in a cache so that this cache line can be written back to main memory. This algorithm is implemented on a bus control unit bridging a 50 Mhz multi-processor interconnect bus with a 33 Mhz peripheral component interconnect bus through an asynchronous interface. All data being transferred between the multi-processor interconnect bus and the peripheral component interconnect bus must pass through the input/output cache on the bus control unit. The algorithm determines a unique locating path to the last used cache lines and from this determines a unique locating path to a memory location which likely contains a least recently used cache line which can then be written back to main memory. Each memory location is identified by a unique locating path which passes through a nodal tree.

Abstract: An output buffer having a data input terminal, a data output terminal, a predriver stage, an output stage and a resistive device. The predriver stage includes a first pull-up transistor and a first pull-down transistor which have control terminals coupled to the data input terminal and have first and second outputs, respectively. The output stage includes a second pull-up transistor and a second pull-down transistor which have control terminals coupled to the first and second outputs, respectively, and have third and fourth output terminals coupled to the data output terminal. The resistive device is coupled between the control terminals of the second pull-up and pull-down transistors.

Abstract: Fine, sub-micron line features and patterns are created in a sensitized layer on a semiconductor wafer by a beam of Gamma-radiation. A continuous stream of such radiation, such as provided by a pellet of Cobalt-60, is collimated into a fine beam by a tapered collimator, and is gated on and off by a shutter mechanism comprising a distortable-surface device and a beam-blocking device. The fine, collimated beam converts points in a gamma-radiation-sensitive layer on a semiconductor wafer. By moving the wafer relative to the beam (or vice-versa), patterns are created in the layer of radiation-sensitive layer for further processing a layer underlying the radiation-sensitive layer.

Abstract: In a method and apparatus for selective convolutional interleaving or de-interleaving of symbols or data bits, a plurality of segments are defined in random access memory, with each segment including a different number of locations for storing symbols. Previously stored symbols are sequentially read out of current locations in the segments respectively, and new symbols are read into the current locations. Next locations in the segments are redesignated as current locations respectively, and the operation is repeated until all of the symbols have been interleaved or de-interleaved. The first location in each segment is designated by a respective segment pointer. The current and next locations are designated as relative offset pointers from the segment pointers, and these locations are incremented by incrementing the offset pointers. Interleaving or de-interleaving operation is determined by the direction in which the segments are sequentially selected for the read/write operations.

Abstract: A Motion Picture Experts Group (MPEG) video/audio data bitstream comprises frames of encoded audio data, each of which includes a plurality of integrally encoded subframes, which are decoded by an audio decoder for presentation. A synchronization unit controls the decoder to skip a subframe if a predetermined decoding time for the subframe is earlier than a current time, and to repeat the subframe if the predetermined decoding time is later than the current time. A typical MPEG audio frame includes 12 subframes, such that skipping or repeating a subframe is 1/12 as noticeable as skipping or repeating an entire frame. A buffer memory stores one or more subframes prior to decoding, such that the subframes can be skipped or repeated by manipulation of a read pointer for the memory.

Abstract: Changing (varying, irregular) resist thickness on semiconductor wafers having irregular top surface topography or having different island sizes, affects the percent reflectance (and absorption efficiency) of incident photolithographic light, and consequently the critical dimensions of underlying features being formed (e.g., polysilicon gates). A low solvent content resist solution that can be applied as an aerosol provides a more uniform thickness resist film, eliminating or diminishing photoresist thickness variations. A top antireflective coating (TAR) also aids in uniformizing reflectance, despite resist thickness variations. The two techniques can be used alone, or together. Hence, better control over underlying gate size can be effected, without differential biasing.

Abstract: A cell placement for a microelectronic integrated circuit includes a plurality of cells interconnected by nets of wiring. A method for estimating routing density in the placement includes superimposing a pattern of contiguous tiles over the placement, with each of the tiles having edges. Bounding boxes are constructed around the nets, and net probable densities are calculated within each bounding box for the wiring required by each net for each edge respectively. The net probable densities are summed to produce total probable densities of wiring required by all of the nets for each edge respectively. The net probable density for each edge is calculated as being equal to a wiring capacity of the edge divided by the sum of the wiring capacity of the edge and all other unobscured edges within the bounding box that are collinear with the edge respectively.

Abstract: A process and resulting product are described for controlling the channeling and/or diffusion of a boron dopant in a P- region forming the lightly doped drain (LDD) region of a PMOS device in a single crystal semiconductor substrate, such as a silicon substrate. The channeling and/or diffusion of the boron dopant is controlled by implanting the region, prior to implantation with a boron dopant,, with noble gas ions, such as argon ions, at a dosage at least equal to the subsequent dosage of the implanted boron dopant, but not exceeding an amount equivalent to the implantation of about 3.times.10.sup.13 argon ions/cm.sup.2 into a silicon substrate, whereby channeling and diffusion of the subsequently implanted boron dopant is inhibited without, however, amorphizing the semiconductor substrate.

Abstract: A method is provided for forming planar, self aligned wells without a high temperature oxidation step to form an ion barrier. The method comprises preparing a substrate with a silicon dioxide-polysilicon-silicon dioxide barrier layer that can be etched to expose different sublayers of the barrier at selected junctures in the production process. A single masking step defines the location of a first set of wells on the prepared substrate. The outer silicon dioxide layer is etched to expose the polysilicon layer at the selected locations, and the substrate is implanted with boron ions to form the first set of wells. Following ion implantation, the substrate photo-resist is removed, and the substrate is exposed to a germanium-silicon mixture under conditions selected to preferentially deposit a germanium-silicon alloy barrier layer on the exposed polysilicon layer.

Abstract: The present invention relates to a method for generating a low pressure plasma circulating in a planar direction within a process enclosure. The invention generates plasma having substantially uniform density characteristics across a planar axis. The invention achieves improved uniformity of the plasma density by delivering more radio frequency power toward the periphery of the circulating plasma than toward the center of the plasma. Increasing the periphery power to the circulating plasma compensates for increased plasma losses due to interaction with the side walls of the process containment enclosure.

Abstract: In an MPEG audio and video signal transmission system in which audio and video signals are encoded in packets which are multiplexed to form a stream for transmission, a receiver system includes a demultiplexer to separate audio and video packets. The header for each packet is parsed, and an error propagation header is inserted with each packet to identify byte count of the packet and an error flag. In a preferred embodiment the error propagation header includes a first byte representing the total byte count and a single bit in a second byte as the error flag. The error propagation header allows errors to be accurately located even in the presence of variable delay introduced by buffers.

Abstract: An electronic system such as a Single-Chip-Module (SCM), a Multi-Chip-Module (MCM), or a Board-Level-Product (BLP) includes a plurality of units which are interconnected by a terminated transmission bus line. Each unit includes a CMOS circuit, a terminated bus line for signal transmission, and a driver/receiver circuit which is spaced from the CMOS circuit on a substrate. A guard ring is formed around at least a part of the CMOS circuit which faces the driver/receiver circuit. The driver/receiver circuit includes a driver for receiving an input logic signal from the CMOS circuit and inducing a corresponding signal onto the bus line, and a receiver for receiving an output signal from the bus line and providing a corresponding output logic signal to the CMOS circuit.

Abstract: A logic circuit and a technique for repairing faulty memory cells internally by employing on-chip testing and repairing circuits in an ASIC system. The test circuit detects column line faults, row faults, and data retention faults in a memory array. The repair circuit redirects the original address locations of the faulty memory lines to the mapped address locations of the redundant column or row lines. This repair scheme includes redundant column lines attached to each of the I/O arrays in the memory array and redundant row lines to replace detected memory faults. These testing and repairing procedures are performed within the chip without the aid of any external equipment.