Abstract: A compact MOS type active device is constructed at least partially in an opening in an insulation layer, such as an oxide layer, above a portion of a semiconductor substrate forming a first source/drain region of the MOS type active device. A semiconductor material, on the sidewall of the opening, and in electrical communication with the portion of the substrate forming the first source/drain region of the device, comprises the channel portion of the MOS device. A second source/drain region, in communication with an opposite end of the channel, is formed on the insulation layer adjacent the opening and in electrical communication with the channel material in the opening. A gate oxide layer is formed over the channel portion and at least partially in the opening, and a conductive gate electrode is then formed above the gate oxide. In this embodiment, the memory transistors are connected to the Vcc bus by resistors.

Abstract: A "personality" card (bias adapter board) is employed to program power supply connections in a DUT (Device Under Test) fixture in an automated test environment. The DUT fixture is designed to provide access to power supply voltages from the automated test equipment (ATE) and to selected (configurable) pins of the device under test. Specific connections are established between designated power supply pins of the DUT and the ATE via the bias adapter card, thereby eliminating the need for a separate, expensive DUT board for each different DUT.

Abstract: A decoder/de-interleaver comprises a de-interleaver for de-interleaving received interleaved encoded data that includes periodic decoder synchronization signals to produce de-interleaved encoded data. A decoder decodes the de-interleaved encoded data to produce output data. The de-interleaver has a latency such that the de-interleaved encoded data is delayed by (B-1) times a period of the decoder synchronization signals plus a constant interval, where B is the interleave depth. A synchronization pulse generator receives the interleaved and encoded data and generates decoder synchronization pulses that are substantially coincident with the decoder synchronization signals. A delay unit is connected between the synchronization pulse generator and the decoder for delaying the decoder synchronization pulses by the constant interval. The decoder thereby receives decoder synchronization pulses that correspond to previous decoder synchronization signals, but functions properly because the relative timing is correct.

Abstract: A camera comprising various arrangements for employing optical elements in association with photosensitive elements are described. In some of the arrangements, the optical elements are formed integrally with a substrate containing the photosensitive elements. In other arrangements, an optical element is mounted to a package, or the like, containing the substrate and photosensitive elements. In other arrangements, two or more optical elements are employed, including conventional refractive elements, refractive focusing elements, and refractive beam splitting elements. Utility as solid state image sensors is discussed. Utility for monochromatic and color imaging is discussed. Various devices based on such camera arrangements and methods of making same are discussed.

Abstract: A method for testing the timing parameters of a system design is presented, especially suited for use in testing for timing violations between the pins of a semiconductor device. A description of the timing constraints of the various modules of a design is written in a common non-technical vernacular, and functions as an input file. A Timing Shell Generator converts the input file description into a simulator-environment-compatible output code-language file description. The output code-language file is operative to implement the timing constraints of the original input file during simulation such that any violations of the prescribed timing constraints are indicated to the tester who can then take appropriate action.

Abstract: A technique for mounting polishing pads to a platen in chemi-mechanical semiconductor wafer polishing apparatus is disclosed. A lower pad is mounted to the platen, and is trimmed to the size of the platen. An upper pad is mounted to the lower pad, and is sized so that an extreme outer edge portion of the upper pad extends beyond the trimmed outer edge of the lower pad. The outer edge portion of the upper pad is deformed downwardly, towards the lower pad. In this manner, polishing slurry is diverted from the pad-to-pad interface. Additionally, an integral annular lip can be formed on the front face of the upper pad, creating a reservoir for slurry to be retained on the face of the upper pad for enhancing residence time of the polishing slurry prior to the slurry washing over the face of the upper pad.

Abstract: The present invention relates to a method of and system for reducing the drive requirements for the input and output pads of an integrated circuit die. An intermediate structure is added between the output connection pad and substrate to reduce the amount of electron charge required to charge the output pad capacitance to a substantially negligible amount. In addition, an intermediate structure may be added between an input connection pad and substrate to reduce the amount of electron charge required to charge the input pad capacitance to a substantially negligible amount. The present invention connects a transistor amplifier driver to the intermediate structure between the output pad and substrate to charge the capacitance that exists between the intermediate structure and substrate so that the voltage potential of the intermediate structure is substantially the same value as the output pad voltage value.

Abstract: A technique for improving the radiation hardness and hot-electron resistance of a CMOS integrated circuit is described whereby undesirable hydrogen ions may be vented through any holes, such as contact holes, in an overlying passivation layer by applying an elevated temperature and/or electrical bias to the integrated circuit die. The elevated temperature and electrical bias serve to accelerate the process by which hydrogen vents from the die. The elimination of unwanted hydrogen significantly reduces threshold shifts in the CMOS integrated circuit, providing greater radiation hardness and hot-electron resistance.

Abstract: Methods of planarizing one or more layers having an irregular top surface topology in a semiconductor device based on an underlying MOS structure are disclosed. Methods of creating doped wells or regions for the underlying MOS structure are also disclosed, using thick oxide growths on the surface of the substrate to mask implantation of ions into the wells. A technique for creating a pair of adjacent complementary oppositely-doped wells, such as for a CMOS structure, using a thick oxide growths as a mask is also disclosed. One of the methods of planarizing the one or more layers involves depositing, densifying and re-flowing a layer of glass on top of the topological layer. Another method of planarizing the one or more layers involves depositing, densifying and chemical-mechanically polishing the deposited and densified glass, thereby avoiding an additional temperature cycle (i.e., for re-flowing the glass) which would adversely affect underlying diffusions.

Abstract: Apparatus for use in cooling an integrated circuit structure. The apparatus includes a heat sink having a first portion configured for thermal engagement with an integrated circuit device and a second portion configured for the dissipation of heat into an ambient fluid, such as air. The heat sink is made from a powdered metal which, in one preferred embodiment, includes copper. The heat sink may be formed from the plurality of discrete layers, each layer having a button projecting from one surface, and a depression formed in an opposing surface. The depression is configured to receive a projecting button portion from another layer. In an alternative embodiment the heat sink includes a plurality of plugs projecting from the generally flat surface.

Abstract: Various forms of micromachined electrostatic microconveyors and useful devices based thereon are described. In one embodiment, a tube shaped conveyor is formed by disposing conductors circumferentially about the exterior surface of the tube. The tube is formed of an insulating material (e.g., silicon dioxide). Driving voltages are applied in staggered phase to selected ones of the conductors to provide a travelling electrostatic wave within the tube. Charged particles (or fluid or gas) can be propelled through the tube electrostatically by "riding" the travelling wave. Various aspects of the invention are directed to apparatus making use of the microconveyor to convey particles, gas ions, etc.. Apparatus is described for using gas pressure resulting from the transport of gas ions to do mechanical work (i.e., to operate mechanical actuators.

Abstract: Fine, sub-micron line features and patterns are created in a sensitized layer on a semiconductor wafer by a beam of low wavelength radiation, such as X-rays. The X-ray source emits very low wavelength radiation along a path towards a sensitized surface of a semiconductor wafer. An image mask substrate is disposed in the path of the radiation, and is provided with opaque material on a surface thereof, forming a pattern. The image mask is spaced sufficiently close to the wafer that radiation passing through the mask forms a corresponding pattern in the surface of the wafer. For X-ray radiation, the opaqueing material is gold, tungsten, platinum, barium, lead, iridium, rhodium, or the like.

Abstract: An integrated circuit structure vertically isolated electrically from the underlying substrate is formed in/on a single crystal semiconductor substrate, such as a silicon semiconductor wafer, by first implanting the substrate with a sufficient dosage of noble gas atoms to inhibit subsequent recrystallization of the semiconductor lattice in the implanted region during subsequent annealing, resulting in the formation of an isolation layer comprising implanted noble gas atoms enmeshed with semiconductor atoms in the substrate which has sufficient resistivity to act as an isolation layer. The preferred noble gases used to form such isolation layers are neon, argon, krypton, and xenon. When neon atoms are implanted, the minimum dosage should be at least about 6.times.10.sup.15 neon atoms/cm.sup.2 to inhibit subsequent recrystallization of the silicon substrate. When argon atoms are implanted, the minimum dosage should be at least about 2.times.10.sup.15 argon atoms/cm.sup.2.

Abstract: A method of making, including a method of floorplanning, an integrated circuit includes the separation of electrical logic function cells of the integrated circuit into sets or macros of data path cells, each of which evidence a high level of similarity or repetitiveness in the integrated circuit, and into sets of random logic cells, which each are connected to data path cells but which do not meet topological and connectivity criteria for the data path cells. The data path cells are iteratively sorted according to connectivity requirements and are initially placed on a provisional floor plan of the integrated circuit in a cell-space matrix of rows and columns, the rows being of substantially uniform width to accommodate functional modules of the data path cells, and the rows being of variably height to cooperatively define the spaces of the cell-space matrix.

Abstract: An ASIC type microcircuit package assembly has a die of at least about 20 millimeters square in size and utilizes as a die attach a polymeric adhesive incorporating a conductive filler. Such microcircuit package assemblies are produced by bonding the die to a substrate with the die attach, curing the die attach, and hermetically sealing the die bonded to the substrate. The microcircuit package assemblies thereby produced are characterized by stability at temperatures of up to about 360.degree. C. and under conditions of stress corresponding to a 12 pound pull following 1,000 temperature cycles between -65.degree. and 150.degree. C., and having a moisture level of less than about 5000 ppm.

Abstract: A process of interconnecting a semiconductor device to a substrate wherein solder balls on the semiconductor device are fused with one side of an embedded noble metal foil within a through hole in an interposer structure. Solder balls on the substrate are fused with the metal foil within the structure window on the other side of the metal foil.

Abstract: A random access memory has an access time which is longer than the period of read input signals, for example digital video data signals, such that it cannot respond directly to the input signals. The memory has two read address inputs and two outputs which are arranged as separate channels, each of which can access any location in the memory. The access time of the memory is shorter than two input signal periods. The input signals are applied alternatingly to the read address inputs, and output signals constituted by data stored at addresses corresponding to the input signals are produced at the memory outputs by an arrangement of clocked latches such that, although two input signal periods are used for accessing each memory location, the alternating accessing using two channels enables the memory to produce output signals having the same period (at the same frequency) as the input signals.

Abstract: A novel channel buffer management scheme for a video decoder minimizes the amount of memory allocated to buffer a video bitstream received from a transmission channel. A channel buffer accumulates picture data encoded in a video bitstream received from a fixed rate channel. Picture data is read out of the channel buffer by a video decoder immediately after a predetermined or expected amount of bitstream data is received by the channel buffer. Picture decoding, reconstructing, and displaying operations are synchronized to permit the transfer of picture data from the channel buffer to the decoder whenever all of the data bits comprising a picture are received in the channel buffer. A microcontroller monitors and regulates the operation of the novel channel buffer management scheme to avoid overflow or underflow of bitstream data in the channel buffer.

Abstract: A process for dynamically adjusting the concentration of one or more reactants in a plasma assisted press, such as a plasma etch process or a plasma deposition process, is describe. The concentration of one or more reactants, as well as the concentration of a non-reactive gas, in a plasma enhance process for the formation of an integrated circuit structure is quantitatively monitored by actinometry to derive a ratio of such concentrations of reactant to non-reactant. The concentration of the reactant or reactants in the plasma processing chamber is then maintained in the chamber by adjusting the flow of such reactant or reactants into the chamber based on changes in such ratio based on such continuous quantitative monitoring of the both the concentration of the reactant or reactants and that of the non-reactive (non-changing concentration) component.

Abstract: Improved thermal characteristics are obtained in a multi-layer substrate for mounting a semiconductor device. A prepeg layer disposed in close proximity to or immediately adjacent to a semiconductor device is formed incorporating an integral, thermally-conductive mesh or screen. The prepeg layer is preferably a sandwich structure of two BT-resin layers (films), between which is disposed a copper screen. In this manner, heat is conducted away from an operating device by an integral part of the substrate, without the need for additional slugs or heat sink structures. Utility for multichip modules is also disclosed.