Abstract: An automatic logic-model generation system operates on a schematic database and produces logic models incorporating accurate timing information. A verification process is also performed whereby the model is automatically verified for accuracy.

Abstract: An apparatus and method for mounting and connecting a plurality of integrated circuit chip dice to a printed circuit substrate by means of a small circuit board (such as a Mini-Board) that may be adapted to attach and connect into a plurality of different types of printed circuit board systems. A pattern of conductors that monotonically increases in pitch and width from a central point on a planar structure to the perimeter edge of the structure allows matching of any type of printed circuit board connections. A standard Mini-Board may be fabricated and tested before attaching to an electronic system printed circuit board. Repair and rework is easily facilitated with a minimum amount of damage to a printed circuit board by utilizing the present invention. A plurality of active and passive electronic components may also be attached and connected to the planar structure of the present invention. A hybrid mini-system may be fabricated and tested before connecting it into a system printed circuit board.

Abstract: A transistor gate array includes an active transistor region (50a-50n) of transistor gates all oriented in a single direction. Surrounding the active transistor region on all four sides are input/output regions (52a-52d) each containing a row of input/output transistors. All of the I/O devices on all sides of the array are oriented in the same common direction, which is the same direction as the orientation of the active transistor in the active region. This arrangement allows the use of the benefits of high angle ion implantation with fewer ion implant steps. Where some of the transistors are oriented at right angles to others, as in the prior art, four separate directions of high angle ion implantation are required to avoid degradation of electrical properties. With all transistors, including those of the gate array and those of the input/output devices, all oriented in the same direction, only two directions of high angle ion implantation are required.

Abstract: A process is disclosed for curing a hydrogen silsesquioxane coating material to form SiO.sub.2 by first placing the coating material in a preheated furnace; igniting a plasma ignited in the furnace immediately after insertion of the coating material therein; then raising the temperature of the furnace up to a predetermined curing temperature, while still maintaining the plasma in the chamber; maintaining the coating material at the curing temperature until substantially all of the coating material has cured to form SiO.sub.2 ; and then extinguishing the plasma and cooling the furnace. In another embodiment, the coating material is cured, with or without the assistance of heat and a plasma, in an ultrahigh vacuum, i.e., a vacuum of at least 10.sup.-5 Torr or better, and preferably at least 10.sup.-6 Torr or better.

Abstract: A novel lid for sealing an encapsulant within a cavity of an integrated circuit package is disclosed herein. A ring is formed around a cavity opening, where a semiconductor die is located in an integrated circuit package. A lid, having a radially extending potion biased toward the die, is adapted to engage the cavity opening. According to one embodiment of the invention, a dam ring is disposed on the top surface of an integrated circuit package so as to form the cavity opening. A radially extending potion of the lid is adapted to engage the inner or outer surface of the ring so as to retain the lid in close communication with the cavity opening and seal the encapsulant within the cavity. Alternatively, the lid can be adapted to engage the cavity opening as existing in the top surface of an integrated circuit package. The present invention is especially advantageous in conjunction with ball grid array ("BGA") packages and pin grid array ("PGA") type IC packages.

Abstract: A technique for reducing thermally-induced mechanical stresses on bond pads in semiconductor device assemblies is accomplished by grouping the bond pads into a relatively small (compared to the total area of the die) sub-area within an interior area (generally away from the periphery) of the die. By keeping the bond pad layout small (tightly grouped, or oriented along a single row, or axis), differential thermally induced displacements between the bond pads are minimized, or are controlled in one dimension. Further, the bond pads may be disposed in a small area near the center of thermal expansion (centroid) of the die or near a heat-producing circuit element to minimize absolute thermal displacements of individual bond pads from the centroid or the circuit element. Overlapping sub-area patterns may be used, and grouped bond pads may be used in conjunction with (including overlapping of) traditional die-periphery located bond pads.

Abstract: A novel synchronization scheme for use in connection with digital signal video decoder comprises a pre-parser, a channel buffer, and a post-parser. The pre-parser synchronizes to a multiplexed system bitstream received from a fixed rate channel. The video bitstream component of a multiplexed system bitstream is then extracted and synchronized prior to being transferred bit-serially from the pre-parser to a channel buffer. The post-parser is coupled to the channel buffer and to a video decoder in a series configuration. The post-parser separates the various layers of video data from the video bitstream component. The post-parser performs a translation operation on the video bitstream component and converts the bitstream data into symbol data. The symbol data is subsequently processed by the video decoder so as to reconstruct an originally encoded picture or frame.

Abstract: Industry-standard COT/TAB integrated circuit part carrier frame members are receivable into a shipping tube member in a stack which rests at one end on paired retaining pins and at the other end is retained by a closure member of the shipping tube. As so disposed in the shipping tube, the carrier frames are securely held with virtually no risk that they will slip out of place within the shipping tube. The shipping tube member includes side walls which define plural pairs of apertures spaced along the length of the shipping tube so that: the paired pins may be relocated to adapt the shipping tube to various shipment sizes. The remainder of the shipping tube remains empty to reduce both the cost of carrier frames conventionally used just as filler, as well as reducing shipping costs by eliminating the weight of these filler carrier frames which are shipped empty.

Abstract: An adaptive error detection and correction apparatus for an Asynchronous Transfer Mode (ATM) network device comprises a sensing unit for sensing a congestion condition in the ATM network and a global pacing rate unit for adaptively reducing a maximum allowable transmission ratio of ATM cells containing information to idle ATM cells in response to a sensed congestion condition. A processor stores a number corresponding to a relatively high maximum allowable transmission ratio in the global pacing rate register in the absence of a sensed congestion condition, and stores a number corresponding to a relatively low maximum allowable transmission ratio in the global pacing rate register in response to a sensed congestion condition. A controller adjusts the maximum allowable transmission ratio in accordance with the number stored in the global pacing rate register.

Abstract: An apparatus and method for detecting burnt resist or mask on the surface of a semiconductor integrated circuit wafer during fabrication thereof. A light source and light sensor are utilized to identify the flat matte surface finish of burnt resist or mask and shut down the fabrication process before a large number of semiconductor wafers are ruined. The burnt resist or mask is detected by the lack of reflected light from the surface of the wafer compared with the light reflected from the surface of a known good resist coated wafer.

Abstract: Signals (including probes) from an external system are selectively connected to a plurality of unsingulated dies on a semiconductor wafer with a minimum number of connections and an electronic selection mechanism resident on the wafer. The electronic selection mechanism is connected to the individual dies by conductive lines on the wafer. The electronic selection mechanism is capable of providing the external signals (or connecting the external probe) to a single die or groups of the dies, and electronically "walking through" the entire plurality of unsingulated dies. Redundant conductive lines may be provided. Diodes and/or fuses may be provided in conjunction with the conductive lines, to protect against various faults which may occur in the conductive lines. Redundant electronic selection mechanisms may also be provided to ensure the ability to selectively provide signals to the unsingulated dies.

Abstract: A package for integrated circuit dies is disclosed comprising a ceramic base capable of having an integrated circuit die mounted to a central portion of one surface thereof to provide heat dissipation for the die; a lead frame with a central opening secured to the periphery of the same surface of the ceramic base; a raised frame member secured to both the lead frame and the peripheral portions of the same surface of the ceramic base exposed between the leads on the lead frame; a die mounted to the exposed central portion of the surface of the ceramic base surrounded by the lead frame and the raised frame member, and electrically bonded to leads on the lead frame; and a plastic potting material over and around the edges of the integrated circuit die and in contact with the exposed portion of the surface of the ceramic base adjacent the die, portions of the lead frame; and inner portions of the raised frame member to thereby encapsulate the integrated circuit die.

Abstract: Composite bond pad structure and geometry increases bond pad density and reduces lift-off problems. Bond pad density is increased by laying out certain non-square bond pads which are shaped, sized and oriented such that each bond pad closely conforms to the shape of the contact footprint made therewith by a bond wire or lead frame lead and aligns to the approach angle of the conductive line to which it is connected. Alternating, interleaved, complementary wedge-shaped bond pads are discussed. Bond pad liftoff is reduced by providing an upper bond pad, a lower bond pad and an insulating component between the upper and lower bond pads. At least one opening is provided through the insulating component, extending from the bottom bond pad to the upper bond pad. The at least one opening is aligned with a peripheral region of the bottom bond pad and is filled with conductive material.

Abstract: Various techniques for quantifying polishing performance are disclosed, and provide insight on the progression from a planarization regime to a smoothing regime to a blanket polish back regime, as well as providing a single, definable parameter (Quality Characteristic) for optimizing polishing performance. With these analytical tools in hand, it is possible to create novel structures which absorb polish rate non-uniformities across a wafer, and it is also possible to define and employ a "quick" polish step to clear high spots which will be followed by a subsequent etch step for rapid removal of material.

Abstract: Apparatus for improving ON/OFF switching in high speed digital circuitry is disclosed. The present invention includes apparatus for altering the impedance or capacitive loading of the interconnect. Some embodiments reduce back reflections by raising the impedance of the interconnect to be closer to that of the contact, or raising the capacitive loading, and others improve the culprit-victim problem by filtering out the highest frequency components of the pulse on the culprit interconnect. For the back reflection problem, the apparatus for altering can be formed of elements for altering the capacitance or, alternatively the resistance, of the interconnect. For the culprit-victim problem, the apparatus for altering includes elements which alter the effective capacitance or resistance of the culprit interconnect.

Abstract: A novel configuration for MOS devices employed in a partially generic gate array type chip having large numbers of generally MOS devices. The MOS devices have a non-rectangular configuration and include at least a first and second region of conductivity type differing from the conductivity type of the gate array substrate that are separated by a channel over which an electrode strip such as a gate is formed. The non-rectangular configuration of the MOS devices provides a space savings that permits the presence of a greater number of devices on a single chip as compared to conventional gate array chips. In accordance with another aspect of the invention one or more patternable busses of conductive material, such as polysilicon, interconnect electrode strips of the MOS devices, such as gates strips, that are made of the same conductive material as the busses.

Abstract: A technique for forming bump bonded semiconductor device assemblies is described wherein a die attach structure is disposed between a semiconductor die and a substrate. Bump bonds (conductive bump contacts) are formed between the die and the substrate, outside of the periphery of the die attach structure. The die attach structure has a "rippled" or egg-crate shaped shape or texture characterized by alternating positive and negative peaks. The die is attached (e.g., by an adhesive) to the positive peaks, and the substrate is attached to the negative peaks. The die attach has the effect of anchoring the die to the substrate and absorbing mechanical shocks which would otherwise be transmitted to the conductive bump contacts. This serves to improve the shock resistance of the chip/substrate assembly. The die attach structure can be made to match the coefficient of expansion of the bump bonds as well as that of the die.

Abstract: A method and apparatus for a "self-calibration timing circuit" is utilized to dynamically compensate for inherent performance differences between individual semiconductor dice, and for a wide range of different operating temperature and voltage parameters. The present invention accomplishes this by utilizing circuits which are deposed on the semiconductor die. These circuits consist of a relaxation oscillator running at the natural frequency of the silicon die, a gated counter counting the number of cycles of the relaxation oscillator frequency during a reference clock period to produce a ratio thereof, and a decision circuit that utilizes this ratio to optimize a system clock frequency for best system operation.

Abstract: Poor sidewall coverage of vias in substrates for multi-chip modules is alleviated by forming pillars associated with conductors on an underlying metal wiring layer. In one embodiment, the pillars are disposed underneath the conductors, causing portions of the conductors to be pushed up through an overlying insulating layer towards a metal layer overlying the insulating layer. The pillars can be electrically conductive or insulating, and can be thermally conductive. In another embodiment, the pillars are disposed atop the conductors, thereby extending at least partially through the insulating layer. These pillars are electrically conductive.

Abstract: An integrated circuit includes a plurality of solder balls arrayed on the bottom surface of a package of the integrated circuit. These solder balls provide for surface mounting of the integrated circuit to a circuit board by solder reflow. The array of solder balls can be planarized so that each of the plural solder balls participate in defining a truly planar solder ball contact array for the integrated circuit package. Methods of manufacturing the integrated circuit with a package having planarized solder balls in an array dependent from a bottom surface thereof are set forth. The truly planarized solder ball contact array of the integrated circuit package affords nearly absolute reliability in forming of surface-mount electrical connections between the integrated circuit package and the circuit board on which the package is to mount.