Patents Assigned to LSI Logic
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Patent number: 5436463Abstract: A conformal, substantially uniform thickness layer of photoresist is deposited on a semiconductor wafer by causing photoresist solids to "sediment" out of solution or suspension. Generally, the more conformal the layer, the more uniform the reflectance of the layer and the less variation in underlying feature critical dimension (cd). In order to accommodate possible resulting deviations in photoresist layer thickness causing undesirable reflectance nonuniformities (and cd variations), a top antireflective coating may be applied to the photoresist layer. In the case of a point-by-point lithography process, such as e-beam lithography, the thickness/reflectance variations can be mapped, and exposure doses adjusted accordingly.Type: GrantFiled: June 13, 1994Date of Patent: July 25, 1995Assignee: LSI Logic CorporationInventor: Michael D. Rostoker
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Patent number: 5434750Abstract: A dambar-less leadframe is sandwiched between two printed circuit boards (PCBs). The PCBs form a major portion of the package body, and isolate the leadframe leads from plastic molding compound. In one embodiment, an upper PCB (substrate) is formed as a ring, having an opening containing a heat sink element. A lower PCB is also formed as a ring, and has a smaller opening for receiving a die. The back face of the die is mounted to the heat sink. The exposed front face of the die is wire bonded to inner ends of conductive traces on the exposed face of the lower PCB. The outer ends of the traces are electrically connected to the leadframe leads by plated-through vias extending through the two PCBs. The plated-through vias additionally secure the sandwich structure together. Plastic molding compound is injection/transfer molded over the front face of the die and the bond wires, forming a partially-molded package. In another embodiment, the upper PCB is a solid planar element.Type: GrantFiled: June 18, 1993Date of Patent: July 18, 1995Assignee: LSI Logic CorporationInventors: Michael D. Rostoker, Chok J. Chia, Seng-Sooi Lim
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Patent number: 5432333Abstract: A camera comprising various arrangements for employing optical elements in association with photosensitive elements are described. In some of the arrangements, the optical elements are formed integrally with a substrate containing the photosensitive elements. In other arrangements, an optical element is mounted to a package, or the like, containing the substrate and photosensitive elements. In other arrangements, two or more optical elements are employed, including conventional refractive elements, refractive focusing elements, and refractive beam splitting elements. Utility as solid state image sensors is discussed. Utility for monochromatic and color imaging is discussed. Various devices based on such camera arrangements and methods of making same are discussed.Type: GrantFiled: August 22, 1994Date of Patent: July 11, 1995Assignee: LSI Logic CorporationInventors: Michael D. Rostoker, David E. Sanders
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Patent number: 5428246Abstract: A highly integrated electronic component comprised of a semiconductor body cast into a plastics enclosure. A multiplicity of metallic terminals protrude from the plastic enclosure, and a heat-conducting plate is cast into the plastic enclosure and is in surface contact with an underside of the semiconductor body. Good heat removal and an increase in the mechanical stability for the terminals are achieved by the heat-conducting plate being substantially planar and bearing both against the underside of the semiconductor body and against the underside of the terminals and by the upper side of the heat-conducting plate having a thin, electrically insulating layer.Type: GrantFiled: July 6, 1993Date of Patent: June 27, 1995Assignee: LSI Logic Products GmbHInventor: Hugo Westerkamp
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Patent number: 5424896Abstract: A semiconductor circuit package includes features forming an electrostatic charge distribution network having nodes which are defined by the electrical contact leads of the package for the semiconductor circuit, and which are effectively connected with one another by spark-gaps. In one embodiment electrical leads of the package are provided with pointed protrusions lying in the plane of the electrical leads. Accordingly, an inadvertent electrostatic discharge is distributed throughout the semiconductor circuit at safe voltage levels determined by the characteristics of the spark gaps of the charge distribution network.Type: GrantFiled: August 12, 1993Date of Patent: June 13, 1995Assignee: LSI Logic CorporationInventors: Nicholas F. Pasch, William Gascoyne
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Patent number: 5420752Abstract: The present invention provides a method for fabricating an integrated circuit package, as well the resulting integrated circuit package, which retains a heatsink in close communication with a mold cavity. This precludes any encapsulant from flowing between the heatsink and the inner surface of a mold cavity. As a consequence, the bottom of the heatsink is not encapsulated and is thus exposed. This is accomplished by including posts, attached to the leadframe assembly, which have the function of exerting a downward force on a leadframe assembly and, in turn, on the heatsink. Tie bars, which are nonfunctional parts of a leadframe assembly, can be utilized as posts by bending the posts into an upright position.Type: GrantFiled: August 18, 1993Date of Patent: May 30, 1995Assignee: LSI Logic CorporationInventor: Patrick Variot
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Patent number: 5414831Abstract: An apparatus and method for accessing a plurality of computer devices having common memory or input-output addresses on buses operating at different speeds. The present invention detects a CPU address request and issues a local bus acknowledge thereto which prevents the CPU core logic from processing the instruction on the other buses. The present invention processes the instruction and upon completion thereof, asserts both CPU BOFF and READY signals on the computer system local bus. The CPU receives the BOFF signal, releases control of the local bus and ignores the READY signal. When the present invention releases the asserted BOFF signal, it then ignores the next local bus cycle because this next local bus signal will be the same as the previous bus cycle. The next CPU bus cycle contains the same information as the previous cycle, and the computer system core logic issues appropriate commands to the other bus interface such as an ISA bus.Type: GrantFiled: December 30, 1993Date of Patent: May 9, 1995Assignee: LSI Logic CorporationInventors: Thomas J. Wilson, J. Peter Van Baarsen
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Patent number: 5414222Abstract: An improved multilayer integrated circuit package. The package, which has a plurality of layers of conducting leads, has metal vias which connects leads in a first layer connected to leads in a second layer. The improvement comprises having at least on of the vias with a cross-section such that the via is much larger in a first direction than in a second direction generally perpendicular to the first direction.Type: GrantFiled: August 17, 1993Date of Patent: May 9, 1995Assignee: LSI Logic CorporationInventors: Bidyut K. Sen, Eric S. Tosaya
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Patent number: 5413966Abstract: A trench mask is formed of two dissimilar layers of material deposited over a substrate. The lower of the two layers is an insulating layer such as silicon dioxide or silicon nitride, or combinations of both, and the upper of the two layers is doped or undoped polysilicon. Together, the two layers are patterned in a first etch step to form a trench mask for subsequent etching of trenches in the substrate. The upper layer is deposited to a thickness "t" related to the desired depth "d" of the trenches to be etched. In a second etch step, the trenches are formed in the substrate. In the case of substantially uniform etching of the polysilicon and the substrate, the thickness of the polysilicon is substantially equal to the desired trench depth. In the case of unequal etching of the polysilicon and the substrate, the thickness of the polysilicon is based on the etch rate disparity.Type: GrantFiled: September 9, 1993Date of Patent: May 9, 1995Assignee: LSI Logic CorporationInventor: Philippe Schoenborn
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Patent number: 5410806Abstract: A method and system for producing a plurality of semiconductor device assemblies utilizing a grid array of conductive epoxy for connecting to an electronic system. Conductive epoxy is screen printed in a desired pattern onto a printed wire board of the semiconductor device assembly. The conductive epoxy is B-staged by heating in an oven. The semiconductor device assembly is then placed onto a system printed circuit board wherein the B-staged conductive epoxy is further cured by heat and effectively makes mechanical and electrical connections between the semiconductor device assembly and the system printed circuit board.Type: GrantFiled: September 15, 1993Date of Patent: May 2, 1995Assignee: LSI Logic CorporationInventor: Mark Schneider
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Patent number: 5410805Abstract: A preformed planar structure is interposed between the chip(s) and the substrate in a flip-chip structure, and establishes a minimum gap between the chip(s) and the substrate. Liquid flux may be applied to the preformed planar structure in order that flux is selectively applied to the solder balls (pads) on the chip and the substrate. The preformed planar structure may be provided with through holes in registration with the solder balls on the chip(s) and the substrate. In this case, liquid flux selectively fills the through holes for delivery to the solder balls during soldering. The through holes also aid in maintaining registration of the chip(s) and the substrate. The through holes may be sized to establish a predetermined mechanical structure of solder joints formed by the solder balls when fused together. The preformed planar structure has a planar core and opposing planar faces.Type: GrantFiled: February 10, 1994Date of Patent: May 2, 1995Assignee: LSI Logic CorporationInventors: Nicholas F. Pasch, Vahak K. Sahakian, Conrad J. Dell'Oca
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Patent number: 5410254Abstract: The present invention relates to a system and method of quantitatively evaluating the amount of electrostatic discharge that integrated circuit field effect transistors may endure before material damage results thereto. The system and method utilizes a plurality of test devices, each having certain differences in structure, which are fabricated onto a common integrated circuit substrate for contemporaneous testing of each device under controlled quantitative conditions. The test results may be organized into a "matrix experiment". A matrix experiment comprises a set of experiments where the settings or values of several product or process parameters to be studied are changed from one experiment to another. An orthogonal matrix array may be utilized to enhance the reliability of the data analysis, and may effectively reduce the number of experiments necessary to establish a reliable conclusion from the limited number of tests performed.Type: GrantFiled: March 4, 1993Date of Patent: April 25, 1995Assignee: LSI Logic CorporationInventor: Rosario J. Consiglio
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Patent number: 5410451Abstract: A thin dielectric substrate bearing a plurality of conductive leads has a hole circumscribed by the substrate in which is positioned a die having pads that are bonded to ends of leads carried by the substrate and projecting into the hole for contact with the die pads. The leads include free outer ends that project laterally outwardly and downwardly away from the plane of the substrate for connection to contact pads on a circuit board. The free leads are isolated from pressure applied to the chip on tape assembly after it has been connected to a circuit board by means of a thin self-supporting thermally conductive heat spreader that contacts the side of the die opposite its pads and includes fixed standoff and/or alignment pins that extend through alignment holes in the thin substrate and are in physical contact with a surface of the printed circuit board.Type: GrantFiled: December 20, 1993Date of Patent: April 25, 1995Assignee: LSI Logic CorporationInventors: Emily Hawthorne, John McCormick
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Patent number: 5409863Abstract: An apparatus and method for controlling unwanted spread of adhesive used to attach a semiconductor integrated circuit die to an integrated circuit package assembly. A barrier prevents the adhesive from spreading onto bond finger connections of the integrated circuit package. The barrier may be a solder mask ring outside of and encircling the perimeter of the die attachment area of the package assembly. The barrier is located between the die attachment area and the adjacent bond fingers of the package.Type: GrantFiled: February 19, 1993Date of Patent: April 25, 1995Assignee: LSI Logic CorporationInventor: Keith G. Newman
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Patent number: 5408146Abstract: A driver circuit formed from CMOS material is provided for receiving an input logic signal from an internal CMOS circuit and inducing a corresponding output signal onto a terminated transmission line. The driver circuit comprises a pre-driver invertor having an input and an output. The invertor inverts a logic state of the input logic signal. The driver circuit also includes an output transistor that provides the output signal and has a drain electrically connected to the transmission line. The driver circuit also includes a control circuit for controlling the output signal during a transition of the input logic signal from a first logic state to a second logic state. The driver circuit is physically isolated from the internal CMOS circuit.Type: GrantFiled: January 31, 1992Date of Patent: April 18, 1995Assignee: LSI Logic CorporationInventors: Trung Nguyen, Anthony Y. Wong
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Patent number: 5407524Abstract: The present invention relates to a system and method for detecting the end-point of a layer being removed from a semiconductor wafer by a plasma etching system. The invention determines end-point by referencing first and second positions of matching components of a matching network between a radio frequency source and the plasma etching system chamber. Comparison of a first position representative of chamber load impedance before end-point, and a second position representative of a change in chamber load impedance is utilized to determine end point.Type: GrantFiled: August 13, 1993Date of Patent: April 18, 1995Assignee: LSI Logic CorporationInventors: Roger Patrick, Frank Bose
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Patent number: 5405808Abstract: Improved thermal and/or electrostatic discharge characteristics are realized in cavity-type semiconductor device assemblies by filling the cavity with either a thermally conductive fluid and/or an arc suppressing gas, or combinations thereof. The interior of the cavity, including the die, leads extending into the cavity, and connections between the die and the leads may be coated to provide protection from corrosive and/or electrical characteristics of the cavity-filling fluid (liquid or gas). The fluid may be introduced through a hole in a lid sealing the cavity, and the cavity is filled sufficiently that the fluid is in contact with the die at various spatial orientations of the package. A thermally-conductive fluid substantially filling the cavity provides improved thermal conduction from the die to the package body without the mechanical stress problems (e.g., thermally induced cracking) ordinarily associated with bonding solid materials to the die.Type: GrantFiled: October 26, 1993Date of Patent: April 11, 1995Assignee: LSI Logic CorporationInventors: Michael D. Rostoker, Nicholas F. Pasch, Mark Schneider
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Patent number: 5403228Abstract: A technique for mounting polishing pads to a platen in chemi-mechanical polishing apparatus is disclosed. With two polishing pads, prior to assembly, a seal of material impervious to the chemical action of a polishing slurry is disposed about the perimeter of the interface between the pads. Preferably, the seal is a bead of silicon-based "gasket" material, such as General Electric silicon caulk (RTV) or Dow Corning silicon adhesive, and is disposed in a ring at a radius r' about one inch inward from the perimeter (circumference) of the pads. When the pads are assembled together, the bead squashes and (1) forms a seal, and (2) causes the periphery of the upper pad to curve upward--thereby creating a bowl-like reservoir for increasing the residence time of slurry on the face of the pad prior to overflowing the pad.Type: GrantFiled: July 8, 1993Date of Patent: April 4, 1995Assignee: LSI Logic CorporationInventor: Nicholas F. Pasch
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Patent number: 5404047Abstract: Composite bond pad structure and geometry increases bond pad density and reduces lift-off problems. Bond pad density is increased by laying out certain non-square bond pads which are shaped, sized and oriented such that each bond pad closely conforms to the shape of the contact footprint made therewith by a bond wire or lead frame lead and aligns to the approach angle of the conductive line to which it is connected. Alternating, interleaved, complementary wedge-shaped bond pads are discussed. Bond pad liftoff is reduced by providing an upper bond pad, a lower bond pad and an insulating component between the upper and lower bond pads. At least one opening is provided through the insulating component, extending from the bottom bond pad to the upper bond pad. The at least one opening is aligned with a peripheral region of the bottom bond pad and is filled with conductive material.Type: GrantFiled: December 18, 1992Date of Patent: April 4, 1995Assignee: LSI Logic CorporationInventors: Michael D. Rostoker, Dorothy A. Heim
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Patent number: 5402499Abstract: A multimedia controller apparatus provides for computer programmed volume control and summing of audio signals in an enhanced multimedia environment. The apparatus is capable of receiving and processing inputs from a CD-ROM FM synthesizer, general MIDI audio, microphone, PCM sampled sound, and telephony systems. From these inputs, it produces outputs for PCM sampled sound, telephony systems, and stereo line-out. Additionally, it provides for the integration of telephonic support functions into a multimedia system. The multimedia controller apparatus comprises a volume control portion for receiving and controlling the volume of a plurality of analog input signals. The volume controlled input signals are then combined by an aggregation portion. A telephony processing portion is also provided for processing the telephony input signals. Stereo outputs, mono outputs, digital samplable outputs, and telephony outputs can be formed from the combined analog and telephony signals by an output portion.Type: GrantFiled: August 7, 1992Date of Patent: March 28, 1995Assignee: LSI Logic CorporationInventors: Jerel D. Robison, David D. Miller, Arthur Scott, Yen C. Chang, Edward X. Wang