Abstract: A semiconductor device assembly is made without a molded package by using a tape having a patterned insulating layer and a conductive layer joined thereto. A semiconductor die is seated on the conductive layer and electrically connected to leads of the patterned conductive layer. A body frame is positioned around the die and electrical leads and connections, and an encapsulant material is distributed over the frame and within the frame over the die and electrical leads and connections.

Abstract: A structure is formed on an electronic integrated circuit by altering the electrical characteristics of a diffused region of a substrate through a contact hole (window) in an insulating layer, in proportion to the size of said contact hole, such that the resistance of the diffused region is changed in a known and predictable fashion and may be measured electrically, giving indirect but accurate evidence of contact size in a completely nondestructive fashion. The measurements may be made on completed devices. Method and structure are disclosed.

Abstract: Two or more independently clocked simulators are interconnected in a manner which prevents signal exchange at a time when the internal simulation clocks of the simulators point to different times on a simulated time line. Each simulator transmits to one or more of the other simulators in its network information indicaitng the next point in simulated time at which the transmitting simulator can model a state change which might affect a model part being simulated by the receiving simulator. Blocking means are provided for blocking the receiving simulator from advancing its simulated time clock ahead of the next state change time of the transmitting simulator. The receiving simulator is free, however, to operate at its maximum speed for simulated time spans occurring before the next state change time of the transmitting simulator.

Abstract: In accordance with the present invention, a process monitor circuit and a method for monitoring a process are provided. The process monitor circuit provides first and second logic paths, the first logic path having a delay sensitive to whether the input logic transition is from logic high to logic low, or from logic low to logic high. The second logic path has substantially equal delays for either logic state transition. The two differences in delay between the first and second logic paths under the two logic state transitions are used to monitor the process steps for manufacturing the P and N transistors.

Abstract: Enhanced uniformity of illumination is achieved in photolithography by interposing photochromic glass in the light path between the illuminator light source and a semiconductor wafer. In one embodiment of the invention, the photochromic glass is disposed immediately adjacent and before (upstream of) the mask. In another embodiment of the invention, the photochromic glass is disposed upstream of the mask, and an intermediate lens is disposed between the photochromic glass and the mask. In a still further embodiment of the invention, the photochromic glass is disposed in a reflector behind the illuminator light source. In other embodiments of the invention. The photochromic glass is disposed downstream of the mask. In yet another embodiment of the invention, the photochromic glass is exposed by two or more copies of a mask on a reticle to effect averaging. The photochromic glass is then used as a virtual mask to expose the wafer. Each of the described embodiments has its own advantages.

Abstract: A plastic-packaged semiconductor device, method of making same, and mounting same to a printed circuit board is disclosed. The device has a body, and a plurality of leads extending from the body. Plastic webs are formed between adjacent leads for supporting the leads. Plastic bumps are formed at the ends of the webs, and align with recesses between conductors of wiring patterns on printed circuit boards, aiding in alignment of the device with the board.

Abstract: A method of testing integrated circuits at high operating speeds is provided which is applicable to sequential logic circuits such as ASICs. A general purpose ASIC tester applies test vectors to the integrated circuit under test. The logic input signals are held unchanged and a series of high speed clock signals (a clock burst) are applied to the clock terminals of the integrated circuit. These clock signals are provided at the speed at which it is desired to test the integrated circuit. Then the output terminals are observed to determined if the device is in the expected state (as determined by simulation) after the clock burst. The process is repeated until no further output terminals change state, and then the device may be reinitialized and another series of state changes initiated. Thus every path in the circuit may be tested at high speed by a conventional low speed tester.

Abstract: An improved method to assemble tape packaged integrated circuits includes spot welding a strip of TAB tape to a thin strip of copper called a strip carrier. The strip carrier provides mechanical rigidity to the tape during later processing, including die attachment and lead bonding and solder plating, as well as providing ESD protection since each tape lead is shorted to the strip carrier. The packaged die and the surrounding tape are excised from the strip carrier prior to final testing and the strip carrier is capable of being reused. The strip carriers are of a size and shape to be readily handled by existing integrated circuit handling equipment.

Abstract: A method for determination of the true temperature T and true radiative emissivity of a body at temperature T, using measurements of total energy radiated by the body in two or more adjacent wave length ranges .lambda..sub.1 .ltoreq..lambda..ltoreq..lambda..sub.2 and .lambda..sub.3 .ltoreq..lambda..ltoreq..lambda..sub.4 ; the wave length ranges may partially overlap or may be adjacent but non-overlapping.

Abstract: The processing time for identifying discrete objects in a visual field composed of pixels is reduced by establishing indirect links between points of occurrence in the array and object names in an object designation list.

Abstract: A circuit for detecting erroneous logic outputs due to metastable behavior in multistable devices (i.e. flip flops) includes a digitally programmable delay unit integrally formed on a common substrate with the multistable devices. Strong correlations between the operating characteristics of the programmable delay unit and the multistable devices may be established during tests for different temperatures, power supply settings and fabrication process variations. Such integration and the digital nature of the programmable delay unit enables repeatable test results and strengthens confidence in predictions that are derived from tests conducted to determine the mean time between failure that is to be expected from the multistable devices. In one embodiment, metastable devices of different design are integrally formed on the common substrate so that comparisons can be made among the metastable behaviors of the different designs.

Abstract: Apparatus for an array of digital signal processors that can be reconfigured as a one-dimensional or as a two-dimensional array; and method and apparatus for compensating for inconsistent time delays in signals processed by n-dimensional arrays of signal processors.

Abstract: A high-speed CMOS output buffer reduces transient current surges and provides high output DC drive. The buffer includes a first and a second CMOS inverter connected in parallel. Each of the two CMOS inverters includes an N channel and a P channel transistor. The gates of the transistors in the first inverter are controlled by a first control inverter having a first selected switching threshold voltage. The gate of the P channel transistor in the second inverter is controlled by a second control inverter having a switching threshold voltage higher than that of the first control inverter. The gate of the N channel transistor in the second inverter is controlled by a third control inverter having a switching threshold voltage lower than that of the first control inverter.

Abstract: Disclosed is a digital multiplier-accumulator circuit utilizing a carry save adder tree, pipeline register and carry select adder. Also disclosed is a digital multiplier circuit including a carry save adder tree and a pipeline register.

Abstract: A method to adjust the divisor and dividend, for application to a divider, so that the mantissa part of the divisor is transformed to be within a known limited range. The limiting of the transformed divisor range enables the complexity of the quotient select logic to be reduced accordingly. Once the divisor is restricted to the selected range, the dividend is adjusted proportionally so the quotient is unchanged.

Abstract: A system in which logic and/or memory elements are automatically placed on an integrated circuit ("floorplanning") taking into account the constraints imposed by the logic designer, not only increase the density of the integrated circuit, and the likelihood of routing interconnections among the elements on that circuit, but it also enables the user to quickly modify the floorplan manually, and then graphically display the results of such modifications. By conforming itself to the logic designer's modular, hierarchical design, the system is capable of placing elements at each level of the specified hierarchy, based upon the number of interconnections between elements throughout that hierarchy.

Abstract: An integrated circuit (IC) chip package is formed by extending the overall dimensions of a standard IC on a semiconductor substrate, typically a first silicon wafer, to provide an integral band of semiconductor material therearound on which are formed a series of spaced IC chip input/output pad areas extending along the band. A bottom peripheral edge of a discrete cap of the same semiconductor material, e.g. silicon, is sealingly affixed around an inner periphery of the band inboard of the series of pad areas and outboard of the IC active circuit areas, so that the cap interior spacedly covers the active circuit area and the input/output pad areas are exposed. The caps may be made by photolithography and microetching techniques from a second semiconductor wafer of the same type as the IC wafer. Metallization extends on the first wafer from connect pads on the active circuit area to the extended and exposed input/output pad areas exterior of the cap. The IC may be probed for test purposes prior to capping.

Abstract: Disclosed is a simulation model which facilitates the "real-time" simulation of application specific integrated circuits (ASICs) in the actual digital computer system in which they will be incorporated. Significantly, this invention permits the emulation of an ASIC device, and thus does not require the fabrication of an actual physical specimen of that device. Instead, this invention permits the use of a software model which facilitates debugging of the ASIC device and permits effective generation of system test vectors. Such an approach facilitates the system-level testing of ASIC devices prior to fabrication, by permitting both the generation of system test vectors and the debugging of the internal behavior of such ASIC devices without limiting the flexibility, with respect to other devices in the system, of either simulating such devices in software or utilizing actual physical specimens of such devices.

Abstract: An improved package with J-leads for an integrated circuit is obtained by modifying the package profile so as to relieve the bottom edge to provide space for insertion of a rod to be used as a tool to shape or reshape the curved part of the leads. This permits both easier original manufacturing and faster and better reshaping of bent leads.

Abstract: A gate array is provided in which active areas within the substrate are arranged in alternating columns of opposite conductivity type and symmetrical about the center lines through each column so that CMOS devices can be advantageously formed by allocating only small increments of active area to metal routing. The substrate and well taps are also symmetrical about the column center line. The active area symmetry allows p-channel and n-channel transistors to be combined where the p-channel transistor is on either the right or left, thus increasing the flexibility in placing the elements within the integrated circuit chip.