Abstract: A method is provided for the controlled formation of voids in integrated circuit doped glass dielectric films. The film can be formed of borophosphosilica glass (BPSG) or other types of doped glass. The method involves the steps of providing a substrate on which conductors are formed, depositing a first layer of doped glass to a thickness in a predetermined ratio to the size of the space between conductors, reflowing the first doped glass layer, applying one or more additional doped glass layers to make up for any shortfall in desired total doped glass thickness, and performing a high temperature densification to smooth each additional layer. The method provides for increased integrated circuit speed by controlled formation of voids which have a low dielectric constant and therefore reduce capacitance between adjacent conductors. The method can be performed using existing doped glass deposition and reflow equipment.

Abstract: Damage to the package body and external leads of a leaded semiconductor device assembly is prevented by a carrier assembly. The carrier assembly includes a rigid bottom (lower) plate positively supporting the package body and providing a bottom cover for the external leads. A semi-rigid top (upper) plate positively holds the package body against the bottom plate, prevents movement of the package body with respect to the carrier assembly, and covers the external leads. Fasteners are provided for securing the upper plate to the lower plate, preferably at the four corners of the plates. In this manner, a durable "sandwich" structure is created, with the package disposed between the lower and upper plates and the body and leads well protected against damage.

Abstract: Damage to the pins and ceramic body of pin grid array type semiconductor device assemblies is avoided by providing ceramic bushings in the pin-receiving holes of a boat transport. The bushings elevate the package body above the platform surface of the boat, and also alleviate problems associated with unequal thermal expansion of the metal boat and the ceramic package. In an alternate embodiment, a ceramic insert formed as a square ring encompassing an area roughly equivalent to the area of the package body is provided with holes for receiving the pins, and the boat transport has a cavity for receiving and retaining the ceramic insert.

Abstract: A lead frame for a multiplicity of terminals, in particular of large-scale integrated semiconductor chips, arranged in a very confined space and consisting of metallic conductors which converge from large outer spacings toward the terminals and can be connected to the terminals. The lead frame allows a high number of terminals with a low degree of spacing of the conductors to be produced. The conductors are produced in the outer region by a conventional production method and at their ends pointing toward the terminals by laser cutting of a uniformly metallic material.

Abstract: A fluid distribution head of this invention includes a chamber for fluid flow including a perforated plate. The perforated plate is internally supported by a structural support to avoid deformation of the plate.

Abstract: A contact structure is formed atop a semiconductor wafer at a level whereat it is desired to terminate polishing of a layer overlying the contact structure. When the contact structure becomes exposed to a polishing slurry, an electrical characteristic, such as resistance or impedance, is registered by measuring apparatus. In one embodiment, two or more contact structures are formed atop the wafer, vias are formed through the wafer, and the vias are filled, thereby providing a conductive path from the contact structures to the back side of the wafer. The measuring apparatus probes the filled vias on the back side of the wafer. A change in resistance/impedance indicates that the contact structures have become exposed during polishing, and polishing is terminated. In another embodiment of the invention, one or more contact structures are formed atop the wafer. The measuring apparatus is connected to a probe in the polishing slurry, and to the wafer itself, such as to the back side of the wafer.

Abstract: A semiconductor package is described which has external connection points (pins, pads, etc.) which may be configured from outside of the package. In one embodiment, this is accomplished with programming holes which pass through and form contact surfaces with various conductors within the package. Conductive material is then deposited into selected holes, forming connections between all of the contact surfaces in any hole. In another embodiment, configurability is accomplished via conductive pads disposed on the exterior surface of the package. Conductive jumpers are then used to connect selected pads. An auxiliary externally effected power plane and bus-bar structure are also described.

Abstract: A dambar-less leadframe is sandwiched between two printed circuit boards (PCBs). The PCBs form a major portion of the package body, and isolate the leadframe leads from plastic molding compound. In one embodiment, an upper PCB (substrate) is formed as a square ring, having an opening containing a heat sink element. A lower PCB is also formed as a square ring, and has a smaller opening for receiving a die. The back face of the die is mounted to the heat sink. The exposed front face of the die is wire bonded to inner ends of conductive traces on the exposed face of the lower PCB. The outer ends of the traces are electrically connected to the leadframe leads by plated-through vias extending through the two PCBs. The plated-through vias additionally secure the sandwich structure together. Plastic molding compound is injection/transfer molded over the front face of the die and the bond wires, forming a partially-molded package.

Abstract: A fully-populated Pin Grid Array (PGA) is vacuum-chucked to a pedestal, without mechanical clamping. The pedestal includes a cylindrical shaft having a vacuum passageway extending its length, and a vacuum reservoir block mounted atop the shaft, and an alignment/fixture plate mounted atop the vacuum reservoir block. The alignment/fixture plate is provided with holes extending partially through the plate, at least about its periphery, for receiving the outermost rows/columns of pins of the PGA, while maintaining a vacuum seal. In one embodiment, a central portion of the alignment/fixture plate is provided with a large through-opening for receiving the remaining pins of the PGA. In another embodiment, the central portion of the alignment/fixture plate is provided with a plurality of individual through holes corresponding to the remaining pins of the PGA. In this manner, the PGA is held securely and well aligned within a wire bonder, while avoiding damaging the pins.

Abstract: A structure and a method are provided for fast-decoding a Huffman code using means for recognizing the number of leading 1's in the Huffman codeword up to a predetermined maximum, and means for removing from the Huffman codeword the number of leading 1's recognized. In one embodiment, both JPEG Huffman code AC and DC tables are stored in a random access memory (RAM). In that embodiment, to access the AC code tables, an address is formed by the number of leading 1's recognized and the portion of Huffman code with the number of leading 1's recognized removed. To access the DC code tables, an address is formed by a predetermined code pattern and the Huffman codeword.

Abstract: A technique of gaining direct access to the inputs and outputs of an embedded microprocessor, otherwise buried behind additional logic, is disclosed. Multiplexers are provided for at least the embedded microprocessor inputs and outputs. In a test mode, the multiplexers connect device input and output pads directly to the embedded microprocessor inputs and outputs. In a normal operating mode, the multiplexers connect the additional logic to the input and output pads. Preferably, in order to standardize design criteria, multiplexers are provided on all of the inputs and outputs of the microprocessor which may become embedded behind additional logic. Additionally, it is possible in the test mode to control the additional logic to a well defined state. The invention provides a simple way to isolate the embedded microprocessor from the rest of the logic and test it thoroughly using test vectors that have already been developed for the stand-alone microprocessor.

Abstract: Various techniques of forming isolation structures between adjacent diffusion regions are disclosed. In one technique, a thermally-grown oxide isolation structure is gouged out, and subsequent poly extending into the gouged out isolation structure is substantially level with the diffusion region. In another technique, a trench (bathtub) is formed, lightly oxidized, overfilled with polysilicon or amorphous silicon, gouged out, and thermally treated to form a substantially planar isolation structure. In another technique, an isolation structure exhibiting bird's-heads and bird's-beaks is polished until the bird's-beaks are removed. Gouging of the diffusion area may be permitted to occur. A bipolar transistor structure can be formed in the gouged diffusion area, and will exhibit reduced spacing between the intrinsic base and collector without proportionally reduced spacing between the extrinsic base and the collector.

Abstract: A tool for measuring a gap between two plates for processing semiconductor wafers is provided. The tool has a solenoid for placement upon a first of the two plates. In the hollow cylinder of the solenoid a slug containing a magnet is mounted so that the slug can slide along the axis of the solenoid. The solenoid is connected to an electric circuit to drive an electrical current therethrough to displace the slug toward and into contact with the second plate. An ammeter measures the current through the solenoid. The measured current corresponds to the slug displacement and yields a measurement of the gap between said two plates.

Abstract: Various techniques of forming isolation structures between adjacent diffusion regions are disclosed. In one technique, a thermally-grown oxide isolation structure is gouged out, and subsequent poly extending into the gouged out isolation structure is substantially level with the diffusion region. In another technique, a trench (bathtub) is formed, lightly oxidized, overfilled with polysilicon or amorphous silicon, gouged out, and thermally treated to form a substantially planar isolation structure. In another technique, an isolation structure exhibiting bird's-heads and bird's-beaks is polished until the bird's-beaks are removed. Gouging of the diffusion area may be permitted to occur. A bipolar transistor structure can be formed in the gouged diffusion area, and will exhibit reduced spacing between the intrinsic base and collector without proportionally reduced spacing between the extrinsic base and the collector.

Abstract: Wells are formed in an external surface of a semiconductor device package body. Capacitors are disposed within the wells at least partially, and preferably fully within the body. Cleaning channels are formed underneath the capacitors, for removing residual flux and/or solder.

Abstract: Bond pad lift problems encountered during bonding are alleviated by providing an upper bond pad, a lower bond pad and an insulating component between the upper and lower bond pads. At least one opening is provided through the insulating component, extending from the bottom bond pad to the upper bond pad. The at least one opening is aligned with a peripheral region of the bottom bond pad. Conductive material fills the at least one opening, and electrically connects the top and bottom bond pads. In one embodiment, the at least one opening is a plurality of conductive vias. In another embodiment, the at least one opening is a ring-like opening extending around the peripheral region. In yet another embodiment, the at least one opening is one or more elongated slit-like openings.

Abstract: A microprocessor with embedded cache memory is disclosed. In a "test mode" of operation, caches are accessed directly from the memory interface signals. Direct writing and reading to/from the instruction and data caches allows the testing of the functionality of the cache memory arrays. External memory interface is granted to an external master via a bus arbitration mechanism so that the test mode operation can be utilized.

Abstract: A technique for chemi-mechanical polishing of semiconductor wafers using ultrasonic energy is disclosed. A transducer is mounted in the polishing system, either to a platen to which the polishing pad is mounted, or to a carrier to which the semiconductor wafer is mounted. In either case, relative vibratory motion is established between the wafer and the polishing pad. The transducer may also be mounted within the reservoir containing the platen, carrier and polishing slurry, to agitate the slurry itself. By vibrating the polishing pad relative to the wafer, polish rate and repeatability are enhanced, the polishing process is less sensitive to pad use history, and the pad is somewhat self-conditioning.

Abstract: The surface of an optical element, such as the taking lens in semiconductor photolithographic apparatus, is deformed, in situ, by applying heat to the surface. A recipe for applying the heat to a selected area of the lens surface is developed by either measuring the image projected by the lens and comparing the measured image to the specified (mask) image, or by measuring the contour of the surface of the lens and comparing the measured contour to the lens' specified contour. The heat is applied by a laser, the output of which is focussed and scanned onto the surface of the lens. Method and apparatus are disclosed.

Abstract: An anisotropic polysilicon etching process in Cl.sub.2 /HBr/He is disclosed. The use of HBr allows etching to occur under high poly:oxide selectivity conditions (e.g., above 40:1) that would otherwise produce lateral etching of the poly under the photoresist mask (isotropy). The selectivity of poly:resist is also increased (e.g., above 4:1). Poly sidewall passivation is enhanced without relying on resist redeposition. Gate oxide loss is also minimized, and anisotropy is realized with increased overetch (e.g., 60%). Exemplary process settings are: 1) 250 mTorr, 190 Watts, 0.5 cm gap, 100 sccm Cl.sub.2, 50 sccm HBr and 40 sccm He; and 2) 270 mTorr, 200 Watts, 0.5 cm gap, 80 sccm Cl.sub.2, 55 sccm HBr and 45 sccm He.