Abstract: A radiation hardened MOSFET is fabricated by forming a dielectric layer of boro-phosphosilicate glass (BPSG) over the field oxide layer of the MOSFET. The BPSG covers only a small part of the gate electrode of the MOSFET. The gate electrode of the MOSFET is formed from two layers of polycrystalline silicon so as to prevent contamination of the gate oxide by the BPSG dopants.

Abstract: A digital multiplier is configured from a number of identical circuit "slices" with interconnecting signals arranged such that the need for large wiring channels is eliminated. The resulting multiplier, a hybrid of tree and array multipliers, has many of the space saving characteristics of array multipliers, with many of the speed advantages of tree multipliers. Various parameters of the design are flexible and may be changed by the designer to make speed versus size tradeoffs. The multiplier may be either pipelined or non-pipelined.

Abstract: A metallic or ceramic dam structure surrounding a semiconductor die in a semiconductor device assembly is disclosed. The dam structure forms a cavity containing a potting compound encapsulating the die. The dam structure may also be provided with a flat lid portion, enclosing the cavity and forming a flat, exterior, heat-dissipating surface for the semiconductor device assembly. Further, an additional add-on structure, having heat dissipating fins, may be joined to the dam structure, exterior the semiconductor device assembly, to provide additional heat dissipation. The add-on structure is particularly well-suited to applications where air cooling is available.

Abstract: In the plating of articles, particularly the filling of via-holes (16) in the manufacture of semiconductor devices, a catalyst, for example palladium, is incorporated throughout the body of material (12) to which plating is to be effected, as compared with activating just the surface of the body.

Abstract: Isolation and passivation structures are formed in a single step, after transistor fabrication, by CVD deposition of a layer of oxide or BPSG over the wafer. The passivation/isolation layer overfills trenches formed for isolation and covers the patterned transistor device The layer is subsequently planarized by chem-mech polishing. With only one deposition step involved, to form both isolation structures and a passivation layer, there is significantly less strain on the thermal budget. Process and product by process are disclosed.

Abstract: A highly integrated electronic component comprised of a semiconductor body cast into a plastics enclosure. A multiplicity of metallic terminals protrude from the plastic enclosure, and a heat-conducting plate is cast into the plastic enclosure and is in surface contact with an underside of the semiconductor body. Good heat removal and an increase in the mechanical stability for the terminals are achieved by the heat-conducting plate being substantially planar and bearing both against the underside of the semiconductor body and against the underside of the terminals and by the upper side of the heat-conducting plate having a thin, electrically insulating layer.

Abstract: A technique for at-speed testing of the core logic of a digital integrated circuit device is disclosed. Test patterns are applied to the circuit inputs while applying a "burst" of three clock pulses followed by a "dead cycle"to the pipeline stages between the input logic, the core logic and the output logic. During the dead cycle, changes in the outputs of the device are observed during the dead cycle. Subsequently, a second burst of clock pulses, offset from the first burst, and followed by a dead cycle, is applied with re-initialized test patterns, and the outputs are observed during the dead cycle. Subsequently, a third burst of clock pulses, offset from the first and second bursts, and followed by a dead cycle, is applied with re-initialized test patterns, and the outputs are observed during the dead cycle. The results of the three iterations of the test are stored and merged to provide a valid indication of the performance of the device with a free running clock.

Abstract: A methodology for generating structural descriptions of complex digital devices from high-level descriptions and specifications is disclosed. The methodology uses a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is essentially a series of transformations operating upon various levels of design representations. At each level, the intended meaning (semantics) and formal software manipulations are captured to derive a more detailed level describing hardware meeting the design goals. Important features of the methodology are: capturing the users concepts, intent, specification, descriptions, constraints and trade-offs; architectural partitioning; what-if analysis at a high level; sizing estimation; timing estimation; architectural trade-off; conceptual design with implementation estimation; and timing closure.

Abstract: A radiation hardened NMOS transistor structure suited for application to radiation hardened CMOS devices, and the method for manufacturing it is disclosed. The new transistor structure is characterized by "P" doped guard bands running along and immediately underlying the two bird's beak regions perpendicular to the gate. The transistor and the CMOS structure incorporating it exhibit speed and size comparable to those of conventional non-rad-hard CMOS structure, relatively simple manufacturing, and excellent total-dose radiation hardness.

Abstract: A system for interactive, design and stimulation of an electronic circuit allowing a user to design a circuit by graphical entry and to view full or partial simulation and design results, simultaneously, on a single display window. The user is able to define the form of a display of speed, delay, loading, symbols, simulation input and/or output values on each node and any path of the design. Simulation may be user-defined or other process time.

Abstract: A glass passivation layer is deposited, densified and polished. Thereby an underlying wafer containing substantially defined devices is exposed to a temperature cycle that is sufficient for densification of the glass, and no more. Reflow and its attendant additional temperature cycle are thereby avoided, allowing for smaller, faster devices to be fabricated. Increased control over the ultimate thickness of the glass layer is also provided.

Abstract: A magnet is disposed in proximity to an un-lidded semiconductor package being assembled. When a ferrous lid is placed over the package opening, the magnetic field holds the lid in place, and also holds the package on an assembly boat carrying the package through an oven for hermetic sealing.

Abstract: Wells are formed in an external surface of a semiconductor device package body. Capacitors are disposed within the wells at least partially, and preferably fully within the body. Cleaning channels are formed underneath the capacitors, for removing residual flux and/or solder.

Abstract: A method and a structure are provided for decoding Huffman codes using a random access memory having a size less than twice the total number of codewords decodable. Under this method, the number of leading 1's in a Huffman codeword and the bits of the Huftman code word other than the leading 1's ("remainder") are combined to form an address into the random access memory. Using the fact that, for a given number of leading 1's in a Huffman code, the possible remainder of the Huffman code is no longer than a predetermined number of bits, the size of the random access memory necessary for decoding such Huffman codes can be made optimally small.

Abstract: During the cleaning of CVD chamber walls with an etch gas of NF.sub.3, the reaction chamber walls are heated to above 65.degree. C. while maintaining a relatively low chamber pressure during etching of the chamber with NF.sub.3. Any reaction of the NF.sub.3 with the quartz (SiO.sub.2) walls of the chamber, and with any reaction by-products remaining in the chamber, will not condense on the walls of the chamber, since, at this relatively high temperature, these reaction products will be volatile and will be purged away with the NF.sub.3.

Abstract: A pipelined floating point multiplier is disclosed having the capability of interleaving floating point multiplication with iterative floating point operations (calculations), such as division and square-root taking, by making use of idle stages (pipeline bubbles). This is accomplished with minimal additional circuitry over that required for conventional floating-point multipliers, and does not adversely affect the speed of iterative calculations. Method and apparatus are disclosed.

Abstract: A capacitor is disposed within a semiconductor device assembly atop a plastic layer pad, beneath which passes a pair of leads connected to a semiconductor device. The capacitor is connected to the pair of leads, such as by soldering, spot welding or conductive epoxy through cutouts in the pad. In one embodiment, the cutouts extend into the pad from inner and outer edges thereof. In another embodiment, the cutouts are holes through the pad. A plurality, such as four, capacitors are conveniently disposed atop a corresponding plurality of pads, and are connected to a corresponding plurality of pairs of leads within the semiconductor device assembly. By positioning the capacitor(s) as closely to the semiconductor device as possible, the efficacy of the capacitor(s) is maximized. Method and apparatus are disclosed.

Abstract: In a leadframe supporting a semiconductor device, the tiebar adjacent the mold gate is kinked, or cut and bent, to form a baffle shielding bond wires connecting the semiconductor device to the leadframe from damage by a jet of incoming molding compound. Whether kinked or cut/bent, the baffle extends out of the plane of the leadframe so as to be disposed more-or-less directly in front of the gate.

Abstract: A digital filter, and more particularly a digital filter such as a transversal filter, is disclosed which is comprised of digital filter modules and provided with a function to detect the occurrence of anomalies such as overflow (a state in which excessively large or small absolute values exceeding an allowable limit are produced during arithmetic operations).

Abstract: A structure and a method are provided for fast-decoding a Huffman code using a leading 1's detector for recognizing the number of leading 1's in the Huffman codeword up to a predetermined maximum, so as to provide a class number in accordance with the number of leading 1's recognized, a first logic circuit for providing a "remainder" by removing from the Huffman codeword a number of bits in accordance with the class number, and a second logic circuit for recognizing a special class. In one embodiment, decoding is accomplished by accessing a storage device using an address formed by a table number, a subclass number derived from the class number and all of the bits in the remainder except the least significant bit.