Abstract: A method for forming a multilayer integrated circuit is described wherein the resultant top surface thereof is substantially planar. The method involves first forming a layer of connecting metallization on integrated circuit components formed in a conventional manner. Then a first layer of dielectric is formed on the metallization layer. Next a second dielectric layer is formed on the first dielectric layer. Via areas are then formed by etching the first and second dielectric layers in order to expose selected areas of the first metallization layer, and filled with metal to form vias. A layer of photoresist is deposited on all surfaces. Lastly, the surface is etched using an etchant that etches dielectric, metal and photoresist at substantially the same rate such that said vias are exposed and a planar top surface produced.

Abstract: A general purposes architecture for a digital microcomputer, which includes a central processing unit, random access memory, user-defined dedicated functions and an optional programmable read only memory. Instructions are fetched either externally or from the optional ROM. Data can be fetched externally or internally. Each instruction fetched is interpreted by a general-purpose microengine. The architecture is flexible enough to permit the modular addition, deletion and modification of dedicated functions and macroinstructions (including changes in execution timing and decoding), as well as the testing of memory independently from the rest of the architecture.

Abstract: A CMOS driver circuit for integrated circuits capable of operating in two modes. The first, high speed, mode allows the driver circuit on an integrated circuit device to drive the internal signals of the device to the outside world for standard operation of the integrated circuit devices. The second mode causes the driver circuit to behave as a weak driver for easily testing the integrated circuit.

Abstract: A circuit (40) constructed in accordance with this invention includes a ring oscillator (25) to provide a signal which is dependent on the propagation delays of the inverters (33, 34, 35) comprising the ring oscillator, therefore the frequency of the ring oscillator is inversely dependent upon the propagation delays of the inverter comprising the ring oscillator. Means (37) are provided to determine the propagation delay introduced by the components in the ring oscillator by measuring the frequency of the output signal produced by the ring oscillator which provides a signal to a multiplexer (36) which selects among a number of preset delay components (26) those components which are necessary to ensure that the propagation delay caused by the circuitry (not shown) connected to the input lead (21) of the circuit constructed in accordance with this invention plus the propagation delay introduced by the selectable delay elements is nearly a constant propagation delay.

Abstract: A composite support assembly for an integrated circuit chip includes a rigid lead frame that is attached to a relatively thin flexible tape-like structure. The tape-like structure is etched with inner lead fingers and outer lead fingers to allow a short pitch, high density arrangement of the lead fingers, thereby enabling bond wires that connect an IC chip to the support assembly to be shortened. As a result, a significant increase in the number of leads is realized, using a standard size IC package.

Abstract: Bonding of lead wires between electrical contact points of an integrated circuit and the conductive elements of a flexible tape-like structure on which the integrated circuit is seated is accomplished by means of a vacuum chuck having distributed recesses through which a partial vacuum is applied to the flexible structure. Support elements are provided with the vacuum recesses to ensure that the flexible tape-like structure presents a planar orientation to a bonding tool. The tape-like structure is maintained in a substantially rigid position during the bonding process enabling precision bonding of lead wires.

Abstract: A Gray code counter employs modules of binary bits to form expressions or numbers. The count is sequenced from one expression to the next by changing only one binary bit in one location of an expression. The Gray code counter can be an incrementing counter or an increment/decrement counter. The counter can operate with expressions of several bits, and employs a minimal number of D type flip-flops and logic gates.

Abstract: A bus interface system for communicating between a master bus interface and a plurality of slave bus interfaces includes a plurality of lines extending between the master unit and each of the slave units, the lines including a clock line containing clock signals, a gated clock line containing gated clock signals having a frequency which is a submultiple of the frequency of the clock signals, a data line, a command register line, an active line, and circuitry for exchanging data between the master unit and one of the slave units on the data line under the control of the other lines.

Abstract: The present method provides for formation of isolation oxide without "bird-beak" extensions thereof through the use of a nitride mask in contact with the surface of a semiconductor substrate on both sides of a patterned oxide layer, on which substrate the isolation oxide is grown.

Abstract: An integrated circuit devicer package includes a rigid frame and flexible tape assembly having wire leads between the die attach pad, conductive lead fingers, and the I.C. chip. A dam structure prevents resin flow to ensure proper wire bonding and a wedge prevents electrical shorting. A recognition pattern enables precise wire bonding. A epoxy molding compound is interposed in cavities formed in a Kapton layer to preclude delamination.

Abstract: A circuit (40) constructed in accordance with this invention includes a ring oscillator (25) to provide a signal which is dependent on the propagation delays of the inverters (33, 34, 35) comprising the ring oscillator, therefore the frequency of the ring oscillator is inversely dependent upon the propagation delays of the inverter comprising the ring oscillator. Means (37) are provided to determine the propagation delay introduced by the components in the ring oscillator by measuring the frequency of the output signal produced by the ring oscillator which provides a signal to a multiplexer (36) which selects among a number of preset delay components (26) those components which are necessary to ensure that the propagation delay caused by the circuitry (not shown) connected to the input lead (21) of the circuit constructed in accordance with this invention plus the propagation delay introduced by the selectable delay elements is nearly a constant propagation delay.

Abstract: A process for forming vias in semiconductor structures includes the step of forming a pillar on an underlying dielectric layer prior to deposition of the metallization layer. The pillar is located above the diffusion region preferably and serves to provide substantially equal distances or heights for etching vias from the top planarized surface to the metallization layer deposited over the field oxide region and over the diffusion region.

Abstract: A system for aligning a semiconductor wafer with a mask bearing a pattern to be formed on the wafer, in which both the wafer and the mask bear an alignment mark, and in which light used for alignment is filtered to transmit only in a selected bandwidth, uses a reflector system to gather light reflected from edges of the alignment mark on the wafer. In order to minimize the effect of erroneous alignment signals from standing waves generated when the alignment signal is reflected from a wafer coated with a layer of photoresist, a second filter is placed in the path of light after it has reflected from the target. This second filter transmits a range of the reflected light which does not produce standing waves.

Abstract: A CMOS reset circuit has a reverse biased diode and a latch for latching a p-channel enhancement mode MOSFET on during the first part of the power-on cycle. The p-channel MOSFET is part of a voltage divider which also includes a resistor. When the voltage between p-channel MOSFET and resistor reach the threshold of an n-channel enhancement mode MOSFET, the p-channel MOSFET is switched off. Reset pulses are provided through one or two inverters by a load on the latch.

Abstract: A contact (15) formed in accordance with the present invention includes rounded corners on the upper and lower surface and sloped walls in the dielectric material (10) in which the contact is formed. In one embodiment, a photolithographic mask is formed above the dielectric material (10) using photolithographic techniques well known in the art. Using reactive ion etching techniques, the contact is etched until a small portion of the dielectric material remains to be etched in the contact. The photolithographic mask is then removed. The contact is then completely etched using a reactive ion etching process. Using this technique, the contact formed has rounded upper edges.

Abstract: A Tri-State circuit element is constructed which is uniquely suited for use in large scale integrated circuit devices wherein a relatively large number of such Tri-State circuits are utilized to drive other circuitry contained within the integrated circuit device. One embodiment of a Tri-State circuit is constructed utilizing a single NAND gate (73), a single inverter (74), a single P channel transistor (76), and two N channel transistors (77, 78) yielding a circuit having a propagation delay of only two gate delays and requiring a total of only nine transistors. Another embodiment of this invention is a Tri-State circuit constructed utilizing a single NOR gate (84), a single inverter (83), a single N channel transistor (88), and two P channel transistors (86, 87). In this embodiment of my invention, a total of nine MOS transistors are required, and the propagation delay between the input terminal and the output terminal is equal to two gate delays.