Abstract: A delay compensator circuit is disclosed to compensate for variations in temperature, supply voltage and process. A monitor circuit is further disclosed that allows the monitoring of the delay of a delay element. The delay compensator circuit and monitor circuit lend themselves easily to the ASIC design methodology since they use conventional ASIC building blocks; namely gates, memory elements and delay elements. The delay compensator and monitor use a time base to track variations in circuit parameters by monitoring the delay through a delay element (delay line or sub-circuit). Compensation may be achieved by switching delays in or out of the circuit to be compensated based on variations of temperature, voltage, and process as measured using the time base. The delay compensator permits the designer to control the output hold time independently of the output delay time. The delay compensator enables a latching device to hold the output signal for the required duration after a reference.

Abstract: In one embodiment, an apparatus programmed to automatically form a barrier layer for contacting a metal interconnect layer to one or more exposed N and P type silicon regions on a wafer. The wafer is heated with a direct radiation source, such as a lamp. To equalize the differing emissivities of the N type and P type silicon regions, an opaque layer of refractory metal is first formed on the regions at a temperature below approximately 100.degree. C. A refractory metal deposition process is then conducted at temperatures between 230.degree. C.-425.degree. C. During this higher temperature deposition process, the reducing gas is ramped up with time to increase the deposition rate of the refractory metal as the exothermic reducing reactions increasingly heat the contact areas.

Abstract: A method of testing integrated circuits at high operating speeds is provided which is applicable to sequential logic circuits such as ASICs. A general purpose ASIC tester applies test vectors to the integrated circuit under test. The logic input signals are held unchanged and a series of high speed clock signals (a clock burst) are applied to the clock terminals of the integrated circuit. These clock signals are provided at the speed at which it is desired to test the integrated circuit. Then the output terminals are observed to determined if the device is in the expected state (as determined by simulation) after the clock burst. The process is repeated until no further output terminals change state, and then the device may be reinitialized and another series of state changes initiated. Thus every path in the circuit may be tested at high speed by a conventional low speed tester.

Abstract: A technique for pinpointing and analyzing failures in complex integrated circuits is disclosed. A device-under-test (DUT) is powered up. Using Liquid Crystal (LC) or Photo-Emission (PE) techniques, leakage sites are identified. The leakage sites are associated with suspect circuit elements on the DUT, and candidate I/Os associated with the suspect failing elements are selected for subsequent testing. Using the candidate I/Os, a truncated set of test vectors is created, and applied to the DUT. While the DUT is running the truncated set of test vectors, the suspect elements are rigorously probed to identify failing elements. SEM images are preferably viewed simultaneously. In this manner, a log of failing elements is derived, for circuit or process re-design.

Abstract: A periodic sequence of signals is intiated and provided to a counter. During this time, a pulse (PULSE) is generated. Upon reaching a terminal count the pulse is terminated. The pulse is provided to a delay element which receives at its input a signal (s) entering, processed within or exiting a semiconductor device. The pulse and periodic sequence of signals are initiated by an edge detector detecting a trigger signal (TRIGGER), which may be the signal (s) being delayed. The sequence of signals is generated by a circuit element, such as a ring oscillator, and the periodicity of the sequence of signals is related to the inherent switching speed of the semiconductor device technology. A plurality of delay circuits are provided in a semiconductor device for individually delaying a plurality of signals entering, processed within and exiting the device. A library of delay circuits may pre-designed, and stored for implementation, as needed, in semiconductor devices.

Abstract: A first heat sink disposed immediately below and closely adjacent a semiconductor chip in a semiconductor chip assembly is disclosed. The heat sink is a flat metallic or ceramic shim. A second heat sink disposed immediately above and closely adjacent the semiconductor device is disclosed. The second heat sink preferably has a flat surface forming an exterior surface of the semiconductive device assembly . In one embodiment, the second heat sink has pedestals resting atop a plastic layer in a tape-like structure within the semiconductor chip assembly. In a second embodiment, the second heat sink includes an add-on portion that is external to the semiconductor chip assembly. The first heat sink is particularly well-suited to applications where the semiconductor chip assembly is mounted to a thermal mass. The second heat sink is particularly well-suited to applications where air cooling is available.

Abstract: A semiconductor device package and a method of making such a package is described. The package comprises a flexible packaging substrate having a patterned metal layer onto which a semiconductor die is attached and a patterned insulative layer attached to the metal layer. The insulative layer includes an annular epoxy-seal gap. A glob of silicone gel is deposited and cured on the die. A casting frame is connected to the metal layer of the flexible substrate on the same side as the die. A backside moisture-blocking layer of material is attached to an opposed side of the tape. The frame and the backside layer are attached to the metal layer of the flexible substrate using cross-linkable epoxy adhesives. These epoxy adhesives join through the epoxy-seal gap to define an epoxy-seal around the die. A thermoset type of molding compound is then poured into the casting frame to define a moisture resistant package body.

Abstract: A semiconductor device is mounted to one face of a printed wiring board (PWB). A heat sink is mounted to an opposite face of the board, opposite the die. The heat sink has a plurality (at least four) "nubs" protruding through a like plurality of holes in the board in the region of the die. In this manner, the nubs conduct heat from the die, through the board, to the heat sink. Preferably, the nubs are sized and shaped to press fit into the holes. Preferably, the holes are plated. Preferably, the heat sink is formed of powdered metal, such as aluminum, copper or a copper/tungsten alloy. The die is attached to the board by any suitable method, such as epoxy and wire bonding, tape automated bonding (TAB), etc. After the heat sink is mounted to the board, the die is encapsulated with resin. A multi-chip module using the novel heat sink structure is also disclosed.

Abstract: A substrate includes a non-conductive support layer and a plurality "n" of conductive leads disposed on the support layer. The leads are arranged in a generally radial pattern about a central point on the support layer, each of the leads having a width "w" and spaced a distance "d" from one another at their innermost ends, thereby forming a generally square opening of side dimension "s". The substrate accommodates semiconductor dies ranging in size from smaller than the opening, to approximately equal to that of the opening, to substantially larger than the opening, such as four times the size (linear dimension) of the opening. The die is bonded to the substrate. Other elements of a semiconductor device assembly are added to the resulting structure. Method and apparatus are disclosed.

Abstract: A preformed planar structure is interposed between the chip(s) and the substrate in a flip-chip structure, and establishes a minimum gap between the chip(s) and the substrate. Liquid flux may be applied to the preformed planar structure in order that flux is selectively applied to the solder balls (pads) on the chip and the substrate. The preformed planar structure may be provided with through holes in registration with the solder balls on the chip(s) and the substrate. In this case, liquid flux selectively fills the through holes for delivery to the solder balls during soldering. The through holes also aid in maintaining registration of the chip(s) and the substrate. The through holes may be sized to establish a predetermined mechanical structure of solder joints formed by the solder balls when fused together. The preformed planar structure has a planar core and opposing planar faces.

Abstract: An adder array for adding two or more input addends, whose bit lengths are not necessarily matched, and a method of configuring the adder array are disclosed. The addends are organized according to bit weight, and bits of equal weight are added in adder columns. Carry-outs are introduced into subsequent, higher weight adder columns according to delay. Thereby, the delay associated with the addition of the addends is minimized. Method and apparatus is disclosed.

Abstract: A general purpose architecture for a digital microcomputer, which includes a central processing unit, random access memory, user-defined dedicated functions and an optional programmable read only memory. Instructions are fetched either externally or from the optionally ROM. Data can be fetched externally or internally. Each instruction fetched is interpreted by a general-purpose microengine. The architecture is flexible enough to permit the modular addition, deletion and modification of dedicated functions and microinstructions (including changes in execution timing and decoding), as well as the testing of memory independently from the rest of the architecture.

Abstract: A genlock frequency generation system synchronizes a dependent, or controllable, video source to an independent video source, with the capability of reverting to some predetermined default conditions in the event that no coherent independent video signal is found. The genlock frequency generation system is capable of placing a dependent video image in an arbitrary rectangular area overlaying the independent video image. Method and apparatus are disclosed.

Abstract: A digital filter, and more particularly a digital filter such as a transversal filter is disclosed, which is comprised of digital filter modules and provided with a function to detect the occurrence of anomalies such as overflow (a state in which excessively large or small absolute values exceeding an allowable limit are produced during arithmetic operations).

Abstract: A structure for filtering process gases prior to said process gases being allowed to enter a CVD chamber includes improved filter and control means to ensure high purity of the process gases. In one embodiment, a first filter means is located in a first section of a gas line being isolated by valves at both ends of the gas line section. A second filter means is located in a downstream gas line section for further filtering.

Abstract: A vibratory tube-to-tube transfer system for transferring the contents of an input tube to an output tube is disclosed. The system includes an alignment fixture having an input section for receiving an input tube loaded with ICs and an output section for receiving an empty output tube. A support plate supports the alignment fixture and a directional vibrator is affixed to the support plate for vibrating the alignment fixture and effecting the transfer of the contents of the input tube to the output tube. An equal number of input tubes and output tubes, such as eight of each, are accommodated by the transfer system.

Abstract: A high-speed receiver/latch is implemented by incorporating a differential amplifier/comparator directly into the feedback loop of a latch function. Both transparent and edge-triggered variants are possible. The resulting circuit is capable of extremely high-speed operation by virtue of very small setup time and small propagation delay.

Abstract: A preformed planar structure is interposed between the chip(s) and the substrate in a flip-chip structure, and establishes a minimum gap between the chip(s) and the substrate. Liquid flux may be applied to the preformed planar structure in order that flux is selectively applied to the solder balls (pads) on the chip and the substrate. The preformed planar structure may be provided with through holes in registration with the solder balls on the chip(s) and the substrate. In this case, liquid flux selectively fills the through holes for delivery to the solder balls during soldering. The through holes also aid in maintaining registration of the chip(s) and the substrate. The through holes may be sized to establish a predetermined mechanical structure of solder joints formed by the solder balls when fused together. The preformed planar structure has a planar core and opposing planar faces.

Abstract: An arithmetic unit using a digital filter is disclosed, and more particularly an arithmetic unit using a digital filter in which a signal filtered by the digital filter and an original signal are processed to derive therefrom an arithmetic signal.

Abstract: A method of making a plastic-packaged semiconductor device, and mounting same to a printed circuit board is disclosed. The device has a body, and a plurality of leads extending from the body. Plastic webs are formed between adjacent leads for supporting the leads. Plastic bumps are formed at the ends of the webs, and align with recesses between conductors of wiring patterns on printed cirucit boards for aiding in alignment of the device with the board.