Abstract: A method and apparatus are provided for interfacing with a synchronous dynamic memory in which memory commands are provided to the memory. The memory is accessed in response to the memory commands. Read data is captured in a data capture circuit having a delay setting. The delay setting is updated in response to detection of a period of read inactivity of the memory.

Abstract: A method and apparatus are provided for summing DC voltages, which employ at least one native transistor device to add a first DC input voltage to a second DC input voltage to produce a sum output.

Abstract: A library to be used in an ASIC design system includes information to be used for verification of test structures. The library includes information regarding the ability to combine test pins for verification of the test structure and information regarding the sharing of ports for verification of the test structure. A user of the ASIC design system can include custom test structures in the library for verification.

Abstract: A method and circuit allows flexible control for termination of a signal line. The mode of operation of the circuit may be set manually or automatically. A software controller provides software control of the signal line. A bus terminator is tied to the signal line. A feedback line from the bus terminator permits monitoring the logic level on the signal line by the software controller. The modes permit software control of the termination or operator setting of the termination by grounding of the signal line or pulling up the signal line to the power line.

Abstract: A cable isolator is provided for automatically performing cable breaks for testing of host bus adapters. A workstation includes a host bus adapter, such as a Fibre Channel storage controller, to be tested. The host bus adapter is connected to one or more storage modules through the cable isolator. The cable isolator includes two transceivers, one of which is connected to the host bus adapter and the other being connected to the storage modules. The two transceivers are also connected to each other internally. The cable isolator also includes a programmable logic device or controller that is used to enable and disable the two transceivers at set intervals. The one or more output disable signals are then provided to the transceivers to perform the cable break. The cable isolator may be an expansion card installed within the workstation. Thus, the workstation may communicate with the cable isolator through an expansion bus.

Abstract: An apparatus comprising one or more user programmable registers and a circuit configured to compare a predetermined portion of one or more information packets with contents of said one or more user programmable registers.

Abstract: A delay locked loop generates a voltage on a common node as a function of a phase difference between a reference input and a feedback input. A first voltage-controlled delay line coupled between the reference input and the feedback input and has a first delay, which is controlled by the voltage on the common node. A second voltage-controlled delay line is selectively coupled in series with the first delay line, between the reference input and the feedback input, as a function of a test control input. The second delay line has a second delay, which is controlled by the voltage on the common node.

Abstract: An integrated circuit comprises a microprocessor for generating data signals along a data bus by way of an inverter to a plurality of input/output switching buffers. The buffers pass the data signals to a transmission bus for onward transmission to a receiving integrated circuit. A respective drain and source supply power to the buffers. A transition checking circuit monitors the number of data signals on the data bus simultaneously switching from a first to a second logic state and a control circuit counts the number of the simultaneous switching data signals and generates a flag signal when the count exceeds half the number of buffers. The flag signal is applied to the inverter to invert all of the data signals on the bus.

Abstract: A system is provided for channeling high frequency signals through sheet metal containment within an electronic device. In exemplary embodiments of the invention, an electronic device employing the system includes a midplane circuit board. One or more interface modules may be coupled to the midplane circuit board, for example, for providing a high frequency interconnect with other devices such as Fiber Channel or the like. A midplane chassis shield is disposed within the device's housing adjacent to the midplane circuit board so that the interface modules interconnect with the midplane circuit board through apertures formed in the shield wherein the midplane circuit board, midplane chassis shield and interface module cooperate for providing a low impedance tunnel for channeling high frequency signals to ground.

Abstract: An array of disk drives may be mounted onto a backplane that may slide as a single unit into an enclosure, such as a rack mounted enclosure. The backplane may allow the disk drives to be arranged in multiple columns and rows such that the disk drives are generally parallel to each other. Such an arrangement affords excellent airflow around the disk drives and greatly simplifies servicing of the disk array.

Abstract: A reconfigurable memory controller includes a plurality of communicatively coupled memory controllers. The plurality of memory controllers may be configured into a first configuration based on a grouping of memory controllers and then reconfigured into a second configuration based on a different grouping of memory controllers, where the first and second configurations have different performance bandwidths for accessing memory.

Abstract: A method of assembling at least a first integrated circuit and a second integrated circuit into a multi chip module. The first integrated circuit is attached and electrically connected to a first substrate to form a first assembly, which is tested to ensure that it functions properly. The second integrated circuit is attached and electrically connected to a second substrate to form a second assembly, which is also tested to ensure that it functions properly. The first assembly is attached and electrically connected to the second assembly to form the multi chip module.

Abstract: The method and circuit of the present invention compensates a timing change over PVT variations without adverse impact on the system. The method and circuit uses two digital programmable delay circuits which have a Master/Slave relationship. The master programmable delay circuit tracks a delay over PVT and readjusts the delay whenever there is a need for calibration due to PVT variations. The slave programmable delay circuit compensates the timing change by delaying the real clock signal when the master programmable delay circuit completes the delay locking process. The resulting circuit is small, flexible, PVT calibrated, and consumes very little power. It can be used with any reference clock to support various timing requirements at different frequencies.

Abstract: The present invention provides an application specific integrated circuit and a method of operation thereof. In one advantageous embodiment, the application specific integrated circuit includes a programmable logic core having an array of dynamically configurable arithmetic logic units. This particular embodiment further includes a network interface subsystem that includes a media access controller. The network interface is configured to employ a first portion of the programmable logic core that interfaces with the media access controller and that is configurable to process control data. This embodiment further includes a data transmission subsystem associated with a memory device, and configured to employ a second portion of the programmable logic core that stores received data from the network interface subsystem to the memory device and sends transmission data from the memory device to the network interface subsystem in response to an instruction from a host system.

Abstract: A method and apparatus for measuring phase margin of a delay-locked loop (DLL) is provided in which a reference clock is applied to a reference input of the DLL. An auxiliary variable delay is coupled within the DLL and is varied until the DLL becomes unstable. A phase margin output is generated as a function of a value of the variable delay at which the DLL becomes unstable.

Abstract: A circuit which includes the addition of test points and analog circuitry required to perform a four-point measurement technique. Test points are fed to an analog multiplexer which is under control of test logic added to the design to facilitate the testing. The output of the analog multiplexer is fed directly to an n-bit Analog-to-Digital Converter (ADC), when the number of bits is determined by the measurement resolution required for the circuit to be tested. The ADC is controlled by digital test logic instantiated in the design to perform the BIST operation. A known current is injected and held constant during the entire BIST operation, and the BIST logic performs voltage measurements. The voltage differential is compared by the BIST circuitry based on the values obtained from the ADC. Then, a pass/fail bit can be passed to a signal pin on the device to be compared by the ATE.

Abstract: Two new ternary CAM bitcell design options are presented that provide compact layout solutions while maximizing matchline channels routing through the cells. In both layouts, the first inventive layout, an asymmetric layout of the 6T-SRAM bitcell is used to improve ease of layout, density, and performance of ternary CAM cells. In the second inventive layout, n-type diffusions for the SRAM bitcell and the comparison circuit are separated, creating a bitcell having a more even cell aspect ratio.

Abstract: An apparatus comprising (i) one or more input/output cells, (ii) one or more hard macros and (iii) one or more input/output affinity regions. The one or more input/output affinity regions may be disposed between the one or more input/output cells and the one or more hard macros. Each of the one or more input/output affinity regions may be customized as (i) circuitry in a first mode and (ii) routing between the one or more input/output cells and the one or more hard macros in a second mode.

Abstract: A system and method are presented for saving and restoring the state of a diagnostic module in a microprocessor. The diagnostic module contains a complex break state machine, capable of halting the microprocessor at specified breakpoints. These breakpoints are based on combinations of instruction locations and/or data values, along with previous machine states. A problem occurs with prior art diagnostic modules when the processor returns from an exception occurring during a fix-up cycle inserted to handle a data load miss associated with an instruction located in a branch delay slot (the location immediately following a conditional branch instruction). Under these circumstances, the exception handler restores the program counter to the location of the branch instruction, causing the branch to be re-executed. The prior art state machine erroneously updates its internal state a second time when the branch is re-executed.

Abstract: An apparatus comprising a first bus segment, a second bus segment and a switch. The first bus segment may be configured to transfer data in either a first direction or a second direction. The second bus segment may be configured to transfer data in either the first direction or the second direction. The switch may be connected between the first bus segment and the second bus segment. The switch may be configured to transfer data in both the first direction and the second direction simultaneously.