Abstract: A luminaire is disclosed comprising one or more side members having one or more light modules associated therewith and defining a recess. The light module having one or more light sources, one or more light directing members, and a lens enclosing the light sources and directing members in the module. The light directing members can comprise reflector modules of different configurations to provide different light distributions from the associated one or more light sources. The light modules can be configured to cast different light distributions to combine to form the desired light distribution. The light modules can be designed or exchanged to create any desired light distribution from the same side members. The light module can comprise a tray such that the lens is sealed to the tray keeping moisture from entering the module.

Abstract: A solar energy system comprising a defrosting module. The defrosting module includes a first light sensor configured to be located on a solar panel and to produce a first signal which is proportional to the intensity of sunlight reaching the solar panel. The defrosting module includes a second light sensor configured to be located proximate to the solar panel and configured to produce a second signal which is proportional to the intensity of ambient sunlight in the vicinity of the solar panel. The defrosting module includes a control circuit configured to compare the first signal and the second signal and to produce an activation signal when the difference between the first signal and the second signal reaches a threshold value, wherein the activation signal is configured to activate a heater module coupled to the solar panel.

Abstract: An apparatus for controlling clock skew in an integrated circuit (IC) includes timing circuitry operative to generate a clock signal for distribution in the IC and at least one buffer circuit operative to receive the clock signal, or a signal indicative of the clock signal, and to generate a delayed version of the clock signal as an output thereof. The buffer circuit includes at least first and second inverter stages and a resistive-capacitive (RC) loading structure. An output of the first inverter stage is connected to an input of the second inverter stage via the RC loading structure. The buffer circuit has a delay associated therewith that is selectively varied as a function of one or more adjustable characteristics of the RC loading structure. Clock skew in the IC is controlled as a function of the delay of the buffer circuit.

Abstract: In described embodiments, a wide toning-range (WTR) inductive-capacitive (LC) phase locked loop (PLL) provides for a large range of differing oscillation frequencies with a set of individual LC voltage controlled oscillator (VCO) paths. The output of each individual wide range LCVCO path is provided to a multiplexor (MUX), whose output is selected based on a control signal from, for example, a device controller. Each of the set of individual wide range LCVCO paths includes a switch that couples the LCVCO to a loop filter of a voltage tuning module, wherein each switch also receives the control signal to disable or enable the LCVCO path when providing the output signal from the MUX. Each switch is configured so as to minimize leakage current drawn by the LCVCO when disabled, and to reduce or eliminate effects of input capacitance of each dormant LCVCO to the loop dynamics of the PLL.

Abstract: LED lighting fixtures, or luminaires, related components, driver circuit, methods, and software/firmware are described that can provide for among other things, ambient environment sensing, thermal self-monitoring, sensor-based power management, communications, and/or programmability. Driver and lighting circuits configured for electrical loads such as series arrangements of light emitting diodes are also described. Embodiments of PFC stages and driver stages can be combined for use as a power supply, and may be configured on a common circuit board. Power factor correction and driver circuits can be combined with one or more lighting elements as a lighting apparatus. Methods of hysteretic power factor correction start-up are also described.

Abstract: An apparatus comprising a multiplexer circuit, a plurality of bit generation circuits, and a control circuit. The multiplexer circuit may be configured to generate an intermediate signal in response to (i) a plurality of input bits and (ii) a control signal. The plurality of bit generation circuits may each be configured to generate one of the plurality of input bits. The control circuit may be configured to generate the control signal.

Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of sub-chains associated with respective distinct clock domains, and clock domain bypass circuitry configured to selectively bypass one or more of the sub-chains. The scan chain is configurable in a scan shift mode of operation to form a serial shift register that includes fewer than all of the sub-chains with at least a remaining one of the sub-chains being bypassed by the clock domain bypass circuitry so as to not be part of the serial shift register in the scan shift mode. By selectively bypassing portions of the scan chain associated with particular clock domains, the clock domain bypass circuitry serves to reduce test time and power consumption during scan testing.

Abstract: An optical disk playback device comprises one or more lasers, an optical assembly, an optical detector, and controller circuitry coupled to the optical detector. The optical assembly is configured to direct incident light from the one or more lasers so as to form first and second scanning spots on a surface of an optical disk, and is further configured to direct corresponding reflected light from the first and second scanning spots on the surface of the optical disk to the optical detector. The optical detector is configured to process the reflected light from the first and second scanning spots to generate respective first and second data streams, and the controller circuitry is configured to generate a three-dimensional image signal from the first and second data streams.

Abstract: A memory device includes at least one memory cell including a storage element electrically connected with a source potential line. A drive strength of the storage element is controlled as a function of a voltage level on the source potential line. The memory device further includes a clamp circuit electrically connected between the source potential line and a voltage source. The clamp circuit is operative to regulate the voltage level on the source potential line relative to the voltage source. A control circuit of the memory device is connected with the source potential line. The control circuit is operative to adjust the voltage level on the source potential line as a function of an operational mode of the memory device. A coarseness by which the voltage level on the source potential line is adjusted is selectively controlled as a function of at least a first control signal.

Abstract: A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and single and dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs.

Abstract: Methods and systems for managing a device in a Web Based Enterprise Management (“WBEM”) environment. At least a management software component and a device management adapter are reused through receiving a network command from the management software component, and forwarding the network command to the device management adapter for conversion to a device message. The WBEM environment is supported by packaging the device message in a WBEM envelope, and transmitting the device message in the WBEM envelope to a computer system. The computer system comprises the device. Subsequently, a native command based on the device message is issued to the device.

Abstract: An application programming interface (API) implementation that can interface between an application and a programming library. The implementation includes a Function Router Wrapper that receives a formatted string from the application. The formatted string includes a function name element filled with a function name, an input element filled with function input parameters, and an unfilled output element. The Function Router Wrapper converts the formatted string and passes it to a Function Router, which parses the converted formatted string to access the function name and the function input parameters. The Function Router calls a library function based on the accessed information. When the called library function is completed, the Function Router collects generated function outputs and embeds them into the formatted string output element. The Function Router passes the formatted string back up to the Function Router Wrapper, which converts the formatted string and passes it back up to the application.

Abstract: A voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply includes an input stage for receiving the input signal, the input stage including at least first and second nodes, a voltage at the second node being a logical complement of a voltage at the first node. A load circuit is coupled with the input stage, the load circuit being operative to at least temporarily store a signal at the first and/or second nodes which is indicative of a logical state of the input signal. An output stage connected with the second node is operative to generate an output signal which is indicative of a logical state of the input signal. The voltage level translator circuit further includes a compensation circuit connected with the output stage and operative to balance pull-up and pull-down propagation delays in the voltage level translator circuit as a function of a voltage at the first node.

Abstract: Methods and apparatus are provided for computing a probability value of a received value in communication or storage systems. A probability value for a received value in a communication system or a memory device is computed by obtaining at least one received value; identifying a segment of a function corresponding to the received value, wherein the function is defined over a plurality of segments, wherein each of the segments has an associated set of parameters; and calculating the probability value using the set of parameters associated with the identified segment.

Abstract: An apparatus including a first circuit and a second circuit. The first circuit may be configured to store a block of data values arranged in a first order. The first circuit may be further configured to present a plurality of the data values in parallel in response to a plurality of address signals, where the data values are presented in a second order. The second circuit may be configured to generate the plurality of address signals in response to a first signal, a second signal and a third signal. The second circuit generally includes an even number of address generators configured to generate the plurality of address signals in parallel.

Abstract: A data processing system for processing a video stream comprises memory array circuitry, memory access circuitry, and video processing circuitry. The memory array circuitry is characterized by a width and a height. The memory access circuitry is operative to cause, through a series of write operations, a series of two-dimensional data representations of different respective regions in a frame of the video stream to be stored in the memory array circuitry. The write operations occur such that only data missing from the memory array circuitry is written to the memory array circuitry during each write operation and such that the data is written modulo at least one of the width and the height of the memory array circuitry. Lastly, the video processing circuitry is operative to perform block matching on the video stream at least in part utilizing the series of two-dimensional data representations stored in the memory array circuitry.

Abstract: Methods and apparatus for improved calculation of redundancy information in RAID storage controllers. Features and aspects hereof provide for a firmware/software element (FPE) for generating redundancy information in combination with a custom logic circuit (HPE) designed to generate redundancy information. A scheduler element operable on a processor of a storage controller along with the FPE determines which of the FPE and HPE is best suited to rapidly complete a new redundancy computation operation and activates or queues the new operation for performance by the selected component.

Abstract: A method for backing up and restoring data across multiple operating systems executed by a computing product executing computer implemented instructions, wherein each operating system includes a daemon. Embodiments may include receiving a backup initiation trigger from an initial, daemon on an initial operating system. This method may include relaying the backup initiation trigger to other daemons on other operating systems. This method may also include receiving snapshot requests from the other daemons, wherein each of the snapshot requests are requests for snapshots of storage associated with an operating system of one of the other operating systems. This method may further include sending received snapshot requests from the other daemons to a storage controller.