Abstract: Disclosed is a system with multiple virtual machines passing I/O requests via a shared memory space. A flag in shared memory is set to a first state in response to a first hypervisor I/O interrupt to indicate that an I/O processing routine is active (running). I/O requests are retrieved from an I/O queue in the shared memory by the I/O processing routine. Based on an indicator that there are no I/O requests remaining in said I/O queue, the shared flag is set to a second state to indicate that the I/O processing routine is deactivated (sleeping). In response to said shared flag being in the second state, when new I/O requests are going to be made, a second hypervisor I/O interrupt is generated. In response to said shared flag being in said first state, I/O requests are inserted into the I/O queue without generating a second hypervisor I/O interrupt.

Abstract: Disclosed is a technique for providing minimal sequential overhead in a flip-flop circuit. Equalization of setup times is achieved in one embodiment. In addition, delays in clock to Q can be equalized for both rising data transitions and falling data transitions. Large setup times are not required since optimization techniques equalize setup times for both rising and falling data transitions.

Abstract: The present invention is related to systems and methods for characterizing circuit operation, and more particularly to systems and methods for modifying a data decoding process.

Abstract: Programmable nanotube interconnect is disclosed. In one embodiment, a method includes forming a interconnect layer using a plurality of nanotube structures, and automatically altering a route of an integrated circuit based on an electrical current applied to at least one of the plurality of nanotube structures in the interconnect layer. Neighboring interconnect layers separated by planar vias may include communication lines that are perpendicularly oriented with respect to each of the neighboring interconnect layers. The nanotube structure may be chosen from a group comprising a polymer, carbon, and a composite material. A carbon nanotube film may be patterned in a metal layer to form the plurality of nanotube structures. A sputtered planar process may be performed across a trench of electrodes to create the carbon nanotube structures.

Abstract: A circuit includes a PMOS body bias circuit including a PMOS charge pump for generating a positive supply voltage, a PMOS reference voltage generator for providing a PMOS reference voltage, and a PMOS linear voltage regulator circuit for generating a PMOS body bias voltage upon receiving the positive supply voltage and the PMOS reference voltage. The circuit also includes a NMOS body bias circuit including a NMOS charge pump for generating a negative supply voltage, a NMOS reference voltage generator for providing a NMOS reference voltage, and a NMOS linear voltage regulator circuit for generating a NMOS body bias voltage upon receiving the negative supply voltage and the NMOS reference voltage. The PMOS body bias voltage and the NMOS body bias voltage drive bulk of PMOS and NMOS devices in the integrated circuit.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a decoder circuit and a scalar circuit. The decoder circuit is operable to perform a data decoding algorithm by processing at least one decoder message, and the scalar circuit is operable to multiply the decoder message by a variable scalar value.

Abstract: A scan clock modifier, a method of providing a variable scan clock, an IC including a scan clock modifier and a library including a cell of a scan clock modifier. In one embodiment, the scan clock modifier includes: (1) logic circuitry configured to provide at least one selected clock signal based on a test scan clock signal and a first clock control signal, both of the test scan clock signal and the first clock control signal received from test equipment and (2) comparison logic configured to provide a scan clock signal based on the at least one selected clock signal and at least one other clock control signal received from the test equipment, wherein the first and the at least one other clock control signals are different clock control signals.

Abstract: A system and method of creating an extra redundancy in a RAID system is disclosed. In one embodiment, one or more RAID arrays are created. Each RAID array comprises a plurality of disk drives. Further, a respective dedicated hot spare is created for each RAID array. Furthermore, data is copied from each RAID array to the respective dedicated hot spare using a copyback process based on a predetermined controller usage threshold value.

Abstract: A data storage system with redundant SSD cache includes an SSD cache organized into logical stripes, each logical stripe having several logical blocks. The logical blocks of each stripe are organized into logical data blocks and one logical parity block. Data may be written to the SSD cache by performing an exclusive disjunction operation on the logical parity block, the new data and the existing data in logical stripe to update the parity block, then writing the new data over the existing data in a logical data block in the same logical stripe.

Abstract: Techniques using scalable storage devices represent a plurality of host-accessible storage devices as a single logical interface, conceptually aggregating storage implemented by the devices. A primary agent of the devices accepts storage requests from the host using a host-interface protocol, processing the requests internally and/or forwarding the requests as sub-requests to secondary agents of the storage devices using a peer-to-peer protocol. The secondary agents accept and process the sub-requests, and report sub-status information for each of the sub-requests to the primary agent and/or the host. The primary agent optionally accumulates the sub-statuses into an overall status for providing to the host. Peer-to-peer communication between the agents is optionally used to communicate redundancy information during host accesses and/or failure recoveries. Various failure recovery techniques reallocate storage, reassign agents, recover data via redundancy information, or any combination thereof.

Abstract: Described embodiments generate tasks corresponding to each packet received by a network processor. A destination processing module receives a task and determines, based on the task size, a queue in which to store the task, and whether the task is larger than space available within a current memory block of the queue. If the task is larger, an address of a next memory block in a memory is determined, and the address is provided to a source processing module of the task. The source processing module writes the task to the memory based on a provided offset address and the address of the next memory block, if provided. If a task is written to more than one memory block, the destination processing module preloads the address of the next memory block to a local memory to process queued tasks without stalling to retrieve the address of the next memory block.

Abstract: Hardware-based methods and apparatus are provided for inter-track interference mitigation in magnetic recording systems. Inter-track interference (ITI) cancellation data is stored in a memory of a read channel of a magnetic recording system. The memory can be in a write data path or a read data path of the read channel. The inter-track interference cancellation data is optionally provided to an inter-track interference mitigation circuit using at least a portion of a write data path, for example, based on a control signal. The storage of the inter-track interference cancellation data can be in response to a second control signal.

Abstract: A hierarchical interface module includes an assessment unit configured to identify a hierarchical implementation incompatibility of an integrated circuit (IC) partitioned block. Additionally, the hierarchical interface module includes an interface unit configured to substitute a directly registered hierarchical interface structure for the hierarchical implementation incompatibility of the IC partitioned block. A method of interfacing hierarchically and a hierarchical implementation system are also included.

Abstract: Various embodiments of the present invention provide systems and methods for signal offset cancellation. For example, a method for error cancellation is disclosed. The method includes: receiving an input signal that includes a second order error component; applying a transfer function to the processed input to reduce the second order error component; and providing an output signal that is the result of applying the transfer function to the input signal.

Abstract: An apparatus comprising a first sub-arbiter circuit and a second sub-arbiter circuit. The first sub-arbiter circuit may be configured to determine a winning channel from a plurality of channel requests based on a first criteria. The second sub-arbiter circuit may be configured to determine a winning channel received from the plurality of channel requests based on a second criteria. The second sub-arbiter may also be configured to optimize the order of the winning channels from the first sub-arbiter by overriding the first sub-arbiter if the second criteria creates a more efficient data transfer.

Abstract: Methods and structure described herein provide for adjusting an error correction capability of an LDPC error correction code. For example, the system of one embodiment includes a decoder adapted to decode data that has been encoded with a LDPC error correction code. The system also includes a detector communicatively coupled to the decoder and adapted to estimate bit values in the data prior to decoding by the decoder. The detector is further adapted to change bit values based on bit value estimations to reduce the error correction capability of the LDPC error correction code. The reduction in error correction capability is adjustable such that sector failure rates of storage devices may be incrementally analyzed.

Abstract: Various embodiments of the present invention provide systems and methods for data processing system. As one example, a data processing circuit is described that includes an analog to digital converter, an online timing loop, and an offline timing loop. The analog to digital converter receives an analog input and provides a first series of data samples Each bit of the first series of data samples corresponds to the analog input at a time controlled by an updated sampling clock. The online timing loop modifies the updated sampling clock based at least in part upon a processed version of the first series of data samples.

Abstract: Methods and circuits comprising a reliability measurement unit (RMU) for generating log-likelihood ratio (LLR) values corresponding to 1T for use in a soft output Viterbi algorithm (“SOVA”) decoder. The RMU operates with an nT clock signal. 1T signals generated by an add, compare, select circuit (ACS) of the SOVA generates 1T decision data and a path equivalency detector generates 1T path equivalency information for 1T SOVA decoding and applies the 1T data to the RMU operating with an nT clock frequency (1/n'th that of the 1T clock signal). The nT RMU receives a plurality of 1T inputs on each nT clock signal pulse and generates 1T LLR information for use by the SOVA decoder. Other components of the SOVA may also operate using the nT clock signal pulse or may operate using a 1T clock signal.

Abstract: Various embodiments of the present invention provide systems and methods for timing recovery. As an example, timing recovery circuits include: a first digital interpolation circuit, a second digital interpolation circuit, a phase selection circuit, and a sampling clock rotation circuit. The first digital interpolation circuit is operable to receive a data input and to provide a first interpolated output corresponding to a first phase, and the second digital interpolation circuit is operable to receive the data input and to provide a second interpolated output corresponding to a second phase. The phase selection circuit operable to select the first phase for processing, and the sampling clock rotation circuit is operable to move a sampling clock away from the first phase.

Abstract: An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to (i) generate second Galois Field elements by performing a first Galois Field inversion on first Galois Field elements, the first Galois Field inversion being different from a second Galois Field inversion defined by an Advanced Encryption Standard and (ii) generate third Galois Field elements by multiplying the second Galois Field elements by an inverse of a predetermined matrix. The second circuit may be configured to (i) generate fourth Galois Field elements by processing the third Galois Field elements in a current encryption round while in a non-skip mode, (ii) generate fifth Galois Field elements by multiplying the fourth Galois Field elements by the predetermined matrix and (iii) present the fifth Galois Field elements as updated versions of the first Galois Field elements in advance of a next encryption round.