Abstract: Multi-stage crest factor reduction (CFR) techniques are provided for multi-channel multi-standard radio (MSR). A multi-stage crest factor reduction method comprises applying one or more data samples associated with at least one channel of a first technology type to a first individual crest factor reduction block; applying one or more data samples associated with at least one channel of a second technology type to a second individual crest factor reduction block; aggregating outputs of the first and second individual crest factor reduction blocks to generate an aggregated output; and applying the aggregated output to a composite crest factor reduction block. The individual crest factor reduction blocks can be implemented using a sampling rate appropriate for the corresponding technology type. The composite crest factor reduction block operates at a higher sampling rate than the individual crest factor reduction blocks.

Abstract: Software implementations are provided for performing IQ imbalance correction and/or RF equalization. An input signal, x, is processed in software by executing a vector convolution instruction to apply the input signal, x, to a first complex FIR filter that performs one or more of RF equalization and IQ imbalance correction; and executing a vector convolution instruction to apply a conjugate x* of the input signal, x, to a second complex FIR filter that performs the one or more of RF equalization and IQ imbalance correction, wherein the second complex FIR filter is in parallel with the first complex FIR filter. The first and second complex FIR filters have complex coefficients and the input signal comprises a complex signal.

Abstract: The present invention is directed to a method for completing a stripe write operation in a timely fashion to a RAID drive pool which includes an abnormally slow drive. For example, the stripe write operation either completes within a required time interval, or an error is provided to the host/initiator which provides an indication to an application that the stripe write operation did not complete.

Abstract: Crest factor reduction (CFR) techniques are provided using asymmetrical pulses. A crest factor reduction method comprises obtaining one or more data samples; detecting at least one peak in the one or more data samples; performing peak cancellation on the at least one detected peak by applying an asymmetric cancellation pulse to the at least one detected peak: and providing processed versions of the one or more data samples. The asymmetric cancellation pulse is generated, for example, by a minimum phase filter and has a substantially minimum group delay. New peaks associated with peak re-growth are introduced substantially only to the one side of the asymmetric cancellation pulse. The process can optionally rewind by an amount greater than or substantially equal to a group delay of the asymmetric cancellation pulse to address the limited number of pre-cursors that may be present in the asymmetric cancellation pulse.

Abstract: The present invention is directed to a method for pre-emptive read reconstruction. In the method(s) disclosed herein, when a pre-emptive read reconstruction timer times out, if one or more drive read operations for providing requested stripe read data are still pending; and if stripe read data corresponding to the pending drive read operations may be constructed (ex.—reconstructed) based on the stripe read data received before the expiration of the timer, the pending drive read operations are classified as stale, but the pending drive read operations are still allowed to complete rather than being aborted, thereby promoting efficiency of the data storage system in situations when the data storage system includes an abnormal disk drive (ex.—a disk drive which endures random cycles of low read performance).

Abstract: A method of motion estimation (ME) refinement. The method generally includes the steps of (A) generating an initial motion vector (MV) by conducting a first ME on an initial block in a picture, the initial block covering an initial area of the picture, (B) generating a current MV by conducting a second ME on a current block in the picture, (i) the current block covering a subset of the initial area and (ii) the second ME being seeded by the initial MV, (C) generating at least one additional MV by conducting at least one third ME on the current block, the at least one third ME being seeded respectively by at least one neighboring MV spatially adjacent to the current MV and (D) generating a refined MV of the current block by storing in a memory a best among the current MV and the additional MV.

Abstract: Described embodiments provide a network processor that includes a security protocol processor to prevent replay attacks on the network processor. A memory stores security associations for anti-replay operations. A pre-fetch module retrieves an anti-replay window corresponding to a data stream of the network processor. The anti-replay window has a range of sequence numbers. When the network processor receives a data packet, the security hardware accelerator determines a value of the received sequence number with respect to minimum and maximum values of a sequence number range of the anti-replay window. Depending on the value, the data packet is either received or accepted. The anti-replay window might be updated to reflect the receipt of the most recent data packet.

Abstract: A lighting apparatus having a base member and a directional member are shown and described. The base member includes a first surface having a plurality of reflective elements extending therefrom. The base member also including a plurality of openings arranged in a pattern. Each openings is configured to receive a respective light source. The directional member has a portion of a reflective surface positioned relative to at least one opening to reflect light radiating from a lighting source disposed within the opening towards a portion of at least one of the reflective elements extending from the base member.

Abstract: Described embodiments provide an apparatus for calculating an N-point discrete Fourier transform of an input signal having multiple sample values. The apparatus includes at least one input configured to receive the sample values and a counter to count sample periods. Also included are at least two parallel multipliers to multiply each sample value, with each of the multipliers having a corresponding multiplication factor. There is at least one multiplexer to select one of the at least two parallel multipliers. An adder sums the scaled sample values and an accumulator accumulates the summed sample values. N is an integer and the at least two parallel multipliers are selectable based upon the value of N and the value of the sample period count.

Abstract: Data latch circuit and method of low power decision feedback equalization (DFE) system is disclosed. In one embodiment, the data latch circuit of the of a decision feedback equalization (DFE) system includes a first parallel n-channel metal-oxide-semiconductor field-effect transistor (NMOS) pair to input a differential input voltage. The data latch circuit also includes a second parallel NMOS pair coupled to the first parallel NMOS pair to input a decision feedback equalization (DFE) voltage. The data latch circuit further includes a cross-coupled PMOS pair to generate a positive feedback to the first parallel NMOS pair and/or the second parallel NMOS pair. In addition, the data latch circuit includes a cross-coupled NMOS pair to escalate the positive feedback. Furthermore the data latch circuit includes a latching circuit to generate a signal data based on the sinking of a current at an input of the latching circuit and/or the positive feedback.

Abstract: A luminaire is disclosed comprising one or more side members having one or more light modules associated therewith and defining a recess. The light module having one or more light sources, one or more light directing members, and a lens enclosing the light sources and directing members in the module. The light directing members redirecting light emitted from at least one of the one or more light sources to be perpendicular to the lens. One or more of the light directing members can be a reflector or an optic lens. The light modules can be configured to cast different light distributions to combine to form the desired light distribution. The light modules can be designed or exchanged to create any desired light distribution from the same side members. The light module can comprise a tray such that the lens is sealed to the tray keeping moisture from entering the module.

Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells. The scan test circuitry further comprises scan enable timing control circuitry coupled between a scan enable input of the scan test circuitry and scan enable inputs of respective ones of the scan cells. The scan enable timing control circuitry is operative to control timing of a transition between a scan shift configuration of the scan cells and a functional data capture configuration of the scan cells so as to permit testing of the scan cells in the scan shift configuration.

Abstract: A luminaire is disclosed comprising one or more side members having one or more light modules associated therewith and defining a recess. The light module having one or more light sources, one or more light directing members, and a lens enclosing the light sources and directing members in the module. The light directing members redirecting light emitted from at least one of the one or more light sources to be perpendicular to the lens. One or more of the light directing members can be a reflector or an optic lens. The light modules can be configured to cast different light distributions to combine to form the desired light distribution. The light modules can be designed or exchanged to create any desired light distribution from the same side members. The light module can comprise a tray such that the lens is sealed to the tray keeping moisture from entering the module.

Abstract: A hard disk drive or other disk-based storage device comprises a storage disk, a read/write head configured to read data from and write data to the storage disk, and control circuitry coupled to the read/write head and configured to process data received from and supplied to the read/write head and to control positioning of the read/write head relative to the storage disk. The control circuitry comprises a disk controller and read channel circuitry, with the read channel circuitry comprising a read channel memory. The control circuitry is further configured to selectively permit the disk controller to access the read channel memory. For example, the disk controller may be permitted to access the read channel memory only when the read channel circuitry is not performing a read operation.

Abstract: A luminaire is disclosed comprising one or more side members having one or more light modules associated therewith and defining a recess. The light module having one or more light sources, one or more light directing members, and a lens enclosing the light sources and directing members in the module. The light directing members can comprise reflector modules of different configurations to provide different light distributions from the associated one or more light sources. The light modules can be configured to cast different light distributions to combine to form the desired light distribution. The light modules can be designed or exchanged to create any desired light distribution from the same side members. The light module can comprise a tray such that the lens is sealed to the tray keeping moisture from entering the module.

Abstract: Various embodiments of the present invention provide apparatuses and methods for processing data in an oversampled data processing circuit with multiple detectors. For example, an apparatus for processing data is disclosed that includes a first analog to digital converter operable to sample a continuous signal at a first sampling phase to yield a first digital output, a second analog to digital converter operable to sample the continuous signal at a second sampling phase to yield a second digital output, wherein the second sampling phase is different from the first sampling phase, a first detector operable to process the first digital output to yield a first detector output, and a second detector operable to process the second digital output and the first detector output to yield a detected output.

Abstract: Methods and apparatus are provided for validating a detection of RRO address marks. After a potential RRO address mark is detected, a disclosed RROAM validation metric evaluates the energy of the remaining RRO data bits in the servo sector, relative to a predefined energy threshold. In addition, the number of remaining RRO data bits in the servo sector is compared to an expected value. The detected RRO address mark is validated in an exemplary embodiment if the RROAM validation metric satisfies the predefined energy threshold and the proper number of remaining RRO data bits is detected in the servo sector. The potential RRO address mark can optionally be discarded if the potential RRO address mark is not validated.

Abstract: The present invention provides methods and apparatus for accomplishing optical direct write phase shift lithography. A lithography system and method are provided wherein a mirror array is configured to generate vortex phase shift optical patterns that are directed onto a photosensitive layer of a substrate. The lithography methods and systems facilitate pattern transfer using such vortex phase shift exposure patterns.

Abstract: A data processing system comprises a device and device access circuitry. The device is mapped to a first mapped address region and to a second mapped address region. The device access circuitry, in turn, is operative to access the device in accordance with a first set of memory attributes when addressing the device within the first mapped address region and to access the device in accordance with a second set of memory attributes when addressing the device within the second mapped address region. The first set of memory attributes is different from the second set of memory attributes.

Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells, with the scan chain being configured to operate as a serial shift register in a scan shift mode of operation and to capture functional data from at least a portion of the additional circuitry in a functional mode of operation. At least a given one of the scan cells of the scan chain comprises multiplexing circuitry configured to select one of multiple data lines of the scan cell for application to a functional output of the scan cell. For example, the multiplexing circuitry may comprise an output multiplexer configured to select between data outputs of master and slave flip-flops for connection to the functional output of the scan cell responsive to a test mode select.