Patents Assigned to LSI
  • Error-floor mitigation of LDPC codes using targeted bit adjustments
    Patent number: 8448039
    Abstract: Embodiments of the present invention are methods for breaking one or more trapping sets in a near codeword of a failed graph-based decoder, e.g., an LDPC decoder. The methods determine, from among all bit nodes associated with one or more unsatisfied check nodes in the near codeword, which bit nodes, i.e., the suspicious bit nodes or SBNs, are most likely to be erroneous bit nodes. The methods then perform a trial in which the values of one or more SBNs are altered and decoding is re-performed. If the trial does not converge on the decoded correct codeword (DCCW), then other trials are performed until either (i) the decoder converges on the DCCW or (ii) all permitted combinations of SBNs are exhausted. The starting state of a particular trial, and the set of SBNs available to that trial may change depending on the results of previous trials.
    Type: Grant
    Filed: March 10, 2009
    Date of Patent: May 21, 2013
    Assignee: LSI Corporation
    Inventor: Kiran Gunnam
  • Task Backpressure and Deletion in a Multi-Flow Network Processor Architecture
    Publication number: 20130125127
    Abstract: Described embodiments generate tasks corresponding to packets received by a network processor. A source processing module sends task messages including a task identifier and a task size to a destination processing module. The destination module receives the task message and determines a queue in which to store the task. Based on a used cache counter of the queue and a number of cache lines for the received task, the destination module determines whether the queue has reached a usage threshold. If the queue has reached the threshold, the destination module sends a backpressure message to the source module. Otherwise, if the queue has not reached the threshold, the destination module accepts the received task, stores data of the received task in the queue, increments the used cache counter for the queue corresponding to the number of cache lines for the received task, and processes the received task.
    Type: Application
    Filed: November 28, 2012
    Publication date: May 16, 2013
    Applicant: LSI CORPORATION
    Inventor: LSI Corporation
  • STORAGE SYSTEM LOGICAL BLOCK ADDRESS DE-ALLOCATION MANAGEMENT AND DATA HARDENING
    Publication number: 20130124777
    Abstract: A bridge receives a power down command and in response converts the power down command to a data hardening command. The bridge issues the data hardening command to a solid state disk. In response to the data hardening command, data stored on the solid state disk is hardened. The hardening comprises writing data in volatile memory to non-volatile memory. The data that is hardened comprises user data and protected data. The data hardening command optionally comprises one or more of a flush cache command, a sleep command, and a standby immediate command.
    Type: Application
    Filed: December 31, 2012
    Publication date: May 16, 2013
    Applicant: LSI CORPORATION
    Inventor: LSI CORPORATION
  • LIGHTING APPARATUS WITH HEAT DISSIPATION SYSTEM
    Publication number: 20130120987
    Abstract: A lighting apparatus is shown and described. In one aspect, the lighting apparatus includes a light source, a plate, and frame. The light source can include one or more lighting elements that are in thermal communication with the light source. The plate can have a dissipative portion extending outward from a point of thermal communication between the plate and the light source. The frame can at least partially enclose the light source and may also be in thermal communication therewith.
    Type: Application
    Filed: January 8, 2013
    Publication date: May 16, 2013
    Applicant: LSI INDUSTRIES, INC.
    Inventor: LSI INDUSTRIES, INC.
  • APPARATUS TO MANAGE EFFICIENT DATA MIGRATION BETWEEN TIERS
    Publication number: 20130124780
    Abstract: A data storage system having a slow tier and a fast tier maintains hot data on the fast tier by migrating data from the slow tier to reserve space on the fast tier as data becomes hot over time. The system maintains a reserve space table and performs a mass migration of data from the fast tier to the slow tier. Data migration is frequently unidirectional with data migrating from the slow to the fast tier, reducing overhead during normal operation.
    Type: Application
    Filed: November 15, 2011
    Publication date: May 16, 2013
    Applicant: LSI CORPORATION
    Inventors: Anant Baderdinni, Gerald E. Smith, Mark Ish
  • Solid-State Disk Manufacturing Self Test
    Publication number: 20130124932
    Abstract: A Solid-State Disk (SSD) Manufacturing Self Test (MST) capability enables an SSD manufacturer to generate and load tests onto SSDs, run the tests, and gather results. The SSDs self execute the loaded tests when powered up. The self executing is while coupled to a host that loaded the tests or while coupled to a rack unable to load the tests but enabled to provide power to the SSDs. The rack is optionally cost-reduced to enable cost-efficient parallel testing of relatively larger numbers of SSDs for production. The host writes the tests to an ‘input’ SMART log of each SSD, and each SSD writes results to a respective included ‘output’ SMART log. The commands include write drive, erase drive, SATA PHY burn-in, delay, and stress mode. The SSD MST capability is optionally used in conjunction with an SSD virtual manufacturing model.
    Type: Application
    Filed: March 30, 2012
    Publication date: May 16, 2013
    Applicant: LSI CORPORATION
    Inventors: Karl David SCHUH, Karl Huan-Yao KO, Aloysius C. Ashley WIJEYERATNAM, Steven GASKILL, Thad OMURA, Sumit PURI, Jeremy Isaac Nathaniel WERNER
  • RECONFIGURABLE CYCLIC SHIFTER ARRANGEMENT
    Publication number: 20130124590
    Abstract: In one embodiment, a reconfigurable cyclic shifter arrangement has first and second reconfigurable cyclic shifters connected in series that are each selectively and independently configurable to operate in any one of three different modes at a time. In a first mode, the reconfigurable cyclic shifter is configured as four 4×4 cyclic shifters to cyclically shift four sets of four input values. In a second mode, the reconfigurable cyclic shifter is configured as two 8×8 cyclic shifters to cyclically shift two sets of eight input values. In a third mode, the reconfigurable cyclic shifter is configured as one 16×16 cyclic shifter to cyclically shift one set of 16 input values. Because the first and second reconfigurable cyclic shifters are independently configurable, there are nine different configurations of the reconfigurable cyclic shifter arrangement.
    Type: Application
    Filed: November 11, 2011
    Publication date: May 16, 2013
    Applicant: LSI Corporation
    Inventors: Kiran Gunnam, Madhusudan Kalluri
  • DIVIDER CIRCUITRY WITH QUOTIENT PREDICTION BASED ON ESTIMATED PARTIAL REMAINDER
    Publication number: 20130124594
    Abstract: An integrated circuit comprises divider circuitry configured to perform a division operation. The divider circuitry may be part of an arithmetic logic unit or other computational unit of a microprocessor, digital signal processor, or other type of processor. The divider circuitry iteratively determines bits of a quotient over multiple stages of computation. In determining the quotient in one embodiment, the divider circuitry is configured to estimate a partial remainder for a given one of the stages and to predict one or more of the quotient bits for one or more subsequent stages based on the estimated partial remainder so as to allow one or more computations to be skipped for said one or more subsequent stages, thereby reducing power consumption. The integrated circuit may be incorporated in a computer, a mobile telephone, a storage device or other type of processing device.
    Type: Application
    Filed: November 15, 2011
    Publication date: May 16, 2013
    Applicant: LSI Corporation
    Inventors: Prakash Krishnamoorthy, Ramesh C. Tekumalla
  • Systems and methods for dual process data decoding
    Patent number: 8443271
    Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, data processing systems are disclosed that include a data decoding system. The data decoding system includes a data decoder circuit and a simplified maximum likelihood value modification circuit. The data decoder circuit is operable to apply a data decode algorithm to a decoder input to yield a first decoded output and an indication of at least one point of failure of the first decoded output. The simplified maximum likelihood value modification circuit is operable to identify a symbol of the first decoded output associated with the point of failure, and to modify a subset of values associated with the identified symbol to yield a modified decoded output.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: May 14, 2013
    Assignee: LSI Corporation
    Inventors: Fan Zhang, Lei Chen, Zongwang Li, Shaohua Yang, Yang Han, Wu Chang
  • Current-mode logic buffer with enhanced output swing
    Patent number: 8441281
    Abstract: A differential buffer circuit having increased output voltage swing includes a differential input stage including at least first and second transistors, the first and second transistors being operative to receive first and second signals, respectively. The buffer circuit further includes a bias stage connected between the differential input stage and a first voltage source. The bias stage is operative to generate a quiescent current as a function of a third signal supplied to the bias stage. A load circuit is connected between a second voltage source and the differential input stage, first and second differential outputs of the buffer circuit being generated at a junction between the load circuit and the differential input stage. The load circuit includes first and second switching elements coupled with the first and second transistors, respectively.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: May 14, 2013
    Assignee: LSI Corporation
    Inventors: Makeshwar Kothandaraman, Pankaj Kumar, Paul K. Hartley, John Christopher Kriz
  • Systems and methods for error correction using irregular low density parity check codes
    Patent number: 8443250
    Abstract: Various embodiments of the present invention provide systems and methods for generating a code format. One method discussed includes: receiving a first matrix having a row width and a column height that is greater than one; incorporating a circulant into a first column of the first matrix; testing the first column for trapping sets, wherein at least one trapping set is identified; selecting a value to mitigate the identified trapping set; and augmenting the first matrix with a second matrix to yield a composite matrix. The second matrix has the selected value in the first column, and wherein the identified trapping set is mitigated.
    Type: Grant
    Filed: October 11, 2010
    Date of Patent: May 14, 2013
    Assignee: LSI Corporation
    Inventors: Zongwang Li, Yang Han, Shaohua Yang
  • Floating-tap decision feedback equalizer for communication channels with severe reflection
    Patent number: 8442106
    Abstract: An apparatus including a first circuit and a second circuit. The first circuit may be configured to determine values for a predefined metric for a plurality of tap positions within a range covered by a decision feedback equalizer (DFE). The values for a number of taps may be determined in parallel. The second circuit may be configured to set one or more floating taps of the DFE to tap positions based upon the values of the predefined metric. The floating taps in the decision feedback equalizer may be selected adaptively.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: May 14, 2013
    Assignee: LSI Corporation
    Inventors: Wing Faat Liu, Freeman Y. Zhong, Lizhi Zhong, Eric Zhang
  • Systems and methods for hard decision assisted decoding
    Patent number: 8443267
    Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a processing loop circuit having a data detector and a soft decision decoder. The data detector provides a detected output, and the soft decision decoder applies a soft decoding algorithm to a derivative of the detected output to yield a soft decision output and a first hard decision output. The systems further include a queuing buffer and a hard decision decoder. The queuing buffer is operable to store the soft decision output, and the hard decision decoder accesses the soft decision output and applies a hard decoding algorithm to yield a second hard decision output. The data detector is operable to perform a data detection on a derivative of the soft decision output if the soft decision decoder and the hard decision decoder fail to converge.
    Type: Grant
    Filed: April 28, 2009
    Date of Patent: May 14, 2013
    Assignee: LSI Corporation
    Inventors: Hao Zhong, Shaohua Yang, Weijun Tan, Changyou Xu, Yuan Xing Lee
  • Systems and methods for low density parity check data encoding
    Patent number: 8443249
    Abstract: Various embodiments of the present invention provide systems and methods for encoding data. As an example, a data encoding circuit is disclosed that includes a first stage data encoder circuit and a second stage data encoder circuit. The first stage data encoder circuit is operable to provide a first stage output. The first stage data encoder circuit includes a first vector multiplier circuit operable to receive a data input and to multiply the data input by a first sparse matrix to yield a first interim value. The second stage encoder circuit includes a second vector multiplier circuit operable to multiply the first stage output by a second sparse matrix to yield a second interim value.
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: May 14, 2013
    Assignee: LSI Corporation
    Inventors: Zongwang Li, Kiran Gunnam, Shaohua Yang
  • Memory device having memory cells with enhanced low voltage write capability
    Patent number: 8441842
    Abstract: A memory device includes a memory array comprising a plurality of memory cells. At least a given one of the memory cells comprises a pair of cross-coupled inverters and associated write assist circuitry. The write assist circuitry comprises first switching circuitry coupled between a supply node of a device of the first inverter and a supply node of the memory cell, and second switching circuitry coupled between a supply node of a device of the second inverter and the supply node of the memory cell. The first and second switching circuitry are separately controlled such that during a write operation of the memory cell the supply node of one of the devices is connected to the supply node of the memory cell while the supply node of the other device is not connected to the supply node of the memory cell but is instead permitted to float.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: May 14, 2013
    Assignee: LSI Corporation
    Inventors: Vinod Rachamadugu, Setti Shanmukheswara Rao, Satisha Nanjunde Gowda
  • Optical disk playback device with prescan functionality for early detection of surface imperfections
    Patent number: 8441903
    Abstract: An optical disk playback device comprises first and second lasers, an optical assembly, first and second optical detectors, and controller circuitry coupled to the optical detectors. The optical assembly is configured to direct incident light from the first and second lasers so as to form respective leading and trailing scanning spots on a surface of an optical disk, and is further configured to direct corresponding reflected light from the leading and trailing scanning spots on the surface of the optical disk to respective ones of the optical detectors. The controller circuitry is configured to identify a surface imperfection of the optical disk by processing the reflected light associated with the leading scanning spot prior to the trailing scanning spot reaching that surface imperfection.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: May 14, 2013
    Assignee: LSI Corporation
    Inventor: Joseph Michael Freund
  • Systems and methods for out of order processing in a data retry
    Patent number: 8443251
    Abstract: Various embodiments of the present invention provide systems and methods for data processing that includes selectively reporting results out of order or in order.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: May 14, 2013
    Assignee: LSI Corporation
    Inventors: Fan Zhang, Yang Han, Shaohua Yang
  • Variable node processing unit
    Patent number: 8443033
    Abstract: A variable node processing unit with N+1 inputs, having at least a first bank of two-input adders and a separate last bank of two-input adders, where the banks of adders are disposed in series.
    Type: Grant
    Filed: August 4, 2008
    Date of Patent: May 14, 2013
    Assignee: LSI Corporation
    Inventors: Alexander Andreev, Sergey Gribok, Oleg Izyumin
  • RECURSIVE DIGITAL PRE-DISTORTION (DPD)
    Publication number: 20130114762
    Abstract: Recursive digital pre-distortion (DPD) techniques are provided. Digital pre-distortion is performed by applying a signal to a recursive system to generate a state vector; providing the state vector as a feedback value to the recursive non-linear system; and applying the state vector to a second function to generate an output signal, wherein at least one of the recursive system and the second function comprise a non-linear function. The recursive non-linear system can be initialized to a known initial value. The recursive system is defined by a system of non-linear differential equations.
    Type: Application
    Filed: October 26, 2012
    Publication date: May 9, 2013
    Applicant: LSI Corporation
    Inventor: LSI Corporation
  • SERVER DIRECT ATTACHED STORAGE SHARED THROUGH VIRTUAL SAS EXPANDERS
    Publication number: 20130117485
    Abstract: A data storage system includes a first server including: a first plurality of storage disks configured to store data, and a first host bus adapter including a first processor configured to provide a first virtual expander and a first logic component; and a second server including: a second plurality of storage disks configured to store data, and a second host bus adapter including a second processor configured to provide a second virtual expander and a second logic component, wherein the first host bus adapter of the first server is coupled to the second host bus adapter of the second server via a SAS connection, and wherein each of the first plurality of storage disks and the second plurality of storage disks are accessible by each of the first server and the second server.
    Type: Application
    Filed: November 4, 2011
    Publication date: May 9, 2013
    Applicant: LSI CORPORATION
    Inventors: Luiz D. Varchavtchik, Jason A. Unrein, Reid A. Kaufmann