Abstract: Systems and methods for out of order memory management.

Abstract: Methods of complementary pairing of memory cells are described. These methods include two physical memory cells in a complementary pair, a complementary pair of reference cells for each erase block, and a physical complementary pair storing multiple data bits.

Abstract: Methods of complementary pairing of memory cells are described. These methods include two physical memory cells in a complementary pair, a complementary pair of reference cells for each erase block, and a physical complementary pair storing multiple data bits.

Abstract: A power management controller controls a power mode associated with a memory device and includes a logic element operative to provide a power mode control signal. The logic element is responsive to first and second control signals, the second control signal being a delayed version of the first control signal. The first control signal is provided by a processing device, and the power mode control signal transitions (i) inactive before a chip select signal transitions active and/or (ii) active after the chip select signal transitions inactive. The chip select signal controls the memory device, and the power mode control signal controls the power mode associated with the memory device. A corresponding method, computer-readable medium, and electronic system are also disclosed. A method that selects a power control mode associated with the power management controller, which controls a power mode associated with the memory device, is also disclosed.

Abstract: A method for performing motion estimation based on at least a first VOP stored in a memory includes the steps of: receiving a request to read a data block indicative of at least a portion of the first VOP for predicting a second VOP that is temporally adjacent to the first VOP; utilizing a DMA module for determining whether the data block is a UMV block; translating a block address for retrieving at least a portion of the data block from the memory as a function of one or more parameters generated by the DMA module; and generating a complete data block as a function of the portion of the data block retrieved from the memory and the one or more parameters generated by the DMA module.

Abstract: Described embodiments process data packets received that include a source address and at least one destination address. If the destination address is stored in a memory of an I/O adapter, the received data packet is processed in accordance with bridging rules associated with each destination address stored in the I/O adapter memory. If the destination address is not stored in the I/O adapter memory, the I/O adapter sends a task message to a processor to determine whether the destination address is stored in an address table stored in a shared memory of the network processor. The I/O adapter memory has lower access latency than the address table. If the destination address is stored in the address table, the received data packet is processed in accordance with bridging rules stored in the address table and the bridging rules stored in the I/O adapter memory are updated.

Abstract: A method of verifying integrated circuit designs, by constructing a series of atomic generators in a staged, hierarchical order, applying a lowest of the hierarchical generator stages to device level test cases of the verification process, applying a highest of the hierarchical generator stages to system level test cases of the verification process, reusing code written for and used in the lowest hierarchical generator stage in a next higher generator stage, creating a constraint scenario in the highest hierarchical generator stage, and injecting the constraint scenario into a next lower generator stage.

Abstract: A system and method for gate training in a memory system is disclosed. In one embodiment, in a method for calibrating read data strobe gating, a first read command is issued to a memory module. A first DQS gate signal is issued before the beginning of the preamble of a first DQS signal received from the memory module that corresponds to the first read command. A second read command is issued to the memory module such that the preamble of a second DQS signal received from the memory module that corresponds to the second read command is adjacent to the postamble of the first DQS signal. Then, a second DQS gate signal is issued at a preset time after the first DQS gate signal. The second DQS signal is sampled repeatedly to locate the preamble of the second DQS signal.

Abstract: A system, method, and computer program product are provided for inserting a gap in information sent from a drive to a host device. In operation, one or more commands are received at a drive from a host device. Additionally, information is queued to send to the host device. Furthermore, a gap is inserted in the information to send to the host device such that the host device is capable of sending additional commands to the drive.

Abstract: In one embodiment, a (hard-drive) read channel has a (DFIR equalization) filter, whose tap coefficients are adaptively updated. A reset controller monitors an (LLR) signal generated downstream of the filter to automatically determine when to reset the filter, e.g., by reloading an initial set of user-specified tap coefficients. For LLR values, the reset controller determines to reset the filter when the reset controller detects that too many recent LLR values have confidence values that are too low. When implemented in a hard-drive read channel, the reset controller can reset the filter one or more times during read operations within a sector of the hard drive.

Abstract: In a communications system that demultiplexes user data words into multiple sub-words for encoding and decoding within different subword-processing paths, the minimum distance between bit errors in an extrinsic codeword can be increased by having corresponding interleavers/deinterleavers in the different subword-processing paths use different interleaving/deinterleaving algorithms.

Abstract: A system and method for generating a spread spectrum clock signal with a constant ppm offset as a function of a repetition number. A phase interpolator can be configured in association with of a phase-locked loop circuit in order to provide a phase movement from a bit clock generated by the PLL circuit. A repetition number divider computes the repetition number for each time slot in a piece-wise SSC modulation profile. A noise shaping modulator can be employed for modulating a fractional part associated with the repetition number. A repetition counter and a phase accumulator receives an integer part of the repetition number and counts unit interval clock periods equal to a sum of integer and the sigma-delta modulated fractional parts of the repetition number. The phase accumulator can be incremented and/or decremented based on the sign of the spread spectrum direction.

Abstract: A method and circuit to control the intensity of lights, illumination fixtures, and displays using pulses of a fixed duration and a fixed frequency (FD/FF) is provided. In particular, the method may be used to control one more light sources. By varying the number of pulses in a control burst, the total current flowing through the light source may be precisely controlled providing greater accuracy than other methods, such as, for example, PWM or variable pulse frequency. The FD/FF technique may be used in conjunction with any number of light sources, and finds particular application in LED displays and for any type of LED illumination fixture.

Abstract: Described embodiments provide an input/output interface of a network processor that generates a request to store received packets to a system cache. If an entry associated with the received packet does not exist in the system cache, the system cache determines whether a backpressure indicator of the system cache is set. If the backpressure indicator is set, the received packet is written to the shared memory. If the backpressure indicator is not set, the system cache determines whether to evict data from the system cache in order to store the received packet. If an eviction rate of the system cache has reached a threshold, the system cache sets a backpressure indicator and writes the received packet to the shared memory. If the eviction rate has not reached the threshold, the system cache determines an available entry and writes the received packet to the available entry in the system cache.

Abstract: Described embodiments classify packets received by a network processor. A processing module of the network processor generates tasks corresponding to each received packet. A packet classification processor determines, independent of a flow identifier of the received task, control data corresponding to each task. A multi-thread instruction engine processes threads of instructions corresponding to received tasks, each task corresponding to a packet flow of the network processor and maintains a thread status table and a sequence counter for each flow. Active threads are tracked by the thread status table, and each status entry includes a sequence value and a flow value identifying the flow. Each sequence counter generates a sequence value for each thread by incrementing the sequence counter each time processing of a thread for the associated flow is started, and decrementing the sequence counter each time a thread for the associated flow is completed.

Abstract: The present invention is a programmable QC LDPC encoder for encoding user data. The encoder may be configurable for implementation with a read channel. The encoder may include a plurality of barrel shifter circuits. The barrel shifter circuits are configured for generating a plurality of parity bits based on interleaved user bits received by the encoder. The barrel shifter circuits are further configured for outputting the parity bits. The encoder may further include an encoder interleaver memory. The encoder interleaver memory may be communicatively coupled with the barrel shifter circuits and may receive the parity bits output from the barrel shifter circuits. The encoder interleaver may be configured for interleaving the parity bits. Further, the encoder may be configured for outputting the interleaved parity bits to a multiplexer. The barrel shifter circuits may generate the plurality of parity bits via an encoding algorithm: p=u*GT.

Abstract: A clock tree power decoupling system includes a pre-decoupling processor that provides a clock tree that supports a critical timing path condition. The clock tree power decoupling system also includes a clock tree power decoupler having a clock tree module that identifies clock buffers in the clock tree corresponding to synchronous start and end points of the critical timing path condition, and a power decoupling module that inserts a decoupling capacitance proximate the clock buffers in the clock tree, wherein the decoupling capacitance is sized to rectify the critical timing path condition. The clock tree power decoupling system additionally includes a post-decoupling processor that provides a power-decoupled clock-inserted database employing the decoupling capacitance. A method of clock tree power decoupling is also provided.

Abstract: Described embodiments classify packets received by a network processor. A processing module of the network processor generates tasks corresponding to each received packet. A scheduler generates contexts corresponding to tasks received by the packet classification processor from corresponding processing modules, each context corresponding to a given flow, and stores each context in a corresponding per-flow first-in, first-out buffer of the scheduler. A packet modifier generates a modified packet based on threads of instructions, each thread of instructions corresponding to a context received from the scheduler. The modified packet is generated before queuing the packet for transmission as an output packet of the network processor, and the packet modifier processes instructions for generating the modified packet in the order in which the contexts were generated for each flow, without head-of-line blocking between flows.

Abstract: A method for transparent debug of a hardware queue and recreation of an operational scenario comprising: use of a computer device to: monitor a plurality of inputs and outputs from a plurality of hardware queues associated as parts of a design; receive a request to save from an external source; pause one or more hardware queues upon command; receive hardware queue information from at least one of the paused hardware queues; dump said hardware queue information from at least one paused hardware queue; store the hardware queue information in a data storage connected to the computing device; compare the received information to stored data representative of a functional hardware queue; identify errors and failures in each monitored hardware queue from the comparing and; restore the hardware queue to a previous state.

Abstract: Described embodiments provide a packet classifier for a network processor that generates tasks corresponding to each received packet. The packet classifier includes a scheduler to generate contexts corresponding to tasks received by the packet classifier from processing modules of the network processor. The packet classifier processes threads of instructions, each thread of instructions corresponding to a context received from the scheduler, and each thread associated with a data flow. A thread status table has N entries to track up to N active threads. Each status entry includes a valid status indicator, a sequence value, a thread indicator and a flow indicator. A sequence counter generates a sequence value for each data flow of each thread and is incremented when processing of a thread is started, and is decremented when a thread is completed. Instructions are processed in the order in which the threads were started for each data flow.