Abstract: In described embodiments, a transceiver includes an eye monitor and margin detector having one or more samplers with corresponding logic. One or more programmable provisioning parameters are defined based on a pre-defined minimum target operating margin for acceptable noise and jitter margins. For example, two programmable provisioning parameters, phase and voltage, correspond with thresholds for margin samplers placed within the eye. Initially, the transceiver applies equalization, after which an inner eye of the transceiver, as detected by the eye monitor, is relatively open with some margin for supporting channels. If the receiver margin goes below this target margin, the eye closes, which is registered by the samplers. In the presence of spectrally rich input data, if the receiver margin goes below this target margin, an updated adaptation of equalizer or other circuit parameters might be initiated; else, adaptation is not generally required.

Abstract: An apparatus is described that is configured to modify a signal to at least substantially remove a noise portion from the signal. In one or more implementations, the apparatus is a collaborative filtering module that is configured to communicatively couple to a memory array having a plurality of memory cell blocks. The memory array is configured to furnish a signal representative of data stored within the plurality of memory cell blocks. The collaborative filtering module is configured to determine a noise distribution associated with the plurality of memory cell blocks and generate a noise prediction, which is based upon the noise distribution, when a read operation for the plurality of memory cell blocks is issued. The collaborative filtering module is also configured to modify the signal utilizing the noise prediction to at least substantially remove noise from the signal.

Abstract: A hard disk drive or other disk-based storage device comprises a storage disk, a read/write head configured to read data from and write data to the storage disk, and control circuitry coupled to the read/write head and configured to process data received from and supplied to the read/write head. The control circuitry comprises clock adjustment circuitry configured to generate a control signal for adjusting a parameter of a clock signal based at least in part on timing information obtained by detecting a timing pattern on a surface of the storage disk. The control signal is generated utilizing at least a predictive correction control loop, with the clock adjustment circuitry comprising predictive control firmware that implements at least a portion of the predictive correction control loop.

Abstract: An apparatus comprising a preamplifier, a channel, and a controller. The preamplifier may be configured to read/write data to a drive with a read/write head, in response to (i) a plurality of digital control signals multiplexed to be sent/received over a first bus and (ii) one or more analog data signals sent/received over a second bus. The channel may be configured to (i) connect to the first and second bus, and (ii) send/receive the plurality of digital control signals through (a) a plurality of interconnects and (b) the first bus. The controller may be configured to send/receive the digital control signals over the interconnects. The apparatus may be configured to (i) read/write the analog data signals to the drive and (ii) generate the digital control signals, in response to one or more input/output requests received from a drive interface.

Abstract: A computer-aided design method for developing, simulating, and testing a read-channel architecture to be implemented in a VLSI circuit. The method uses a coset operating mode and nonzero-syndrome-based decoding to accelerate the simulation of the read-channel's error-rate characteristics corresponding to different parity-check matrices employed in the read-channel's turbo-decoder, such as a low-density parity-check decoder. The acceleration is achieved through recycling some previously generated log-likelihood-ratio values, which enables the method to sometimes bypass certain time-consuming processing steps therein.

Abstract: A dynamic power recovery system and method are disclosed herein. Additionally, an EDA tool and apparatus configured to perform dynamic power recovery are disclosed.

Abstract: Systems and methods for dynamic storage tiering using snapshot functionality are disclosed. A point-in-time copy of a virtual volume including a storage hot-spot is created; write operations directed to the virtual volume may be redirected to a point-in-time temporary virtual volume. The virtual volume segment, including the hot-spot, is copied from a first storage pool to a second storage pool. Finally, a logical block address mapping of the virtual volume is reconfigured to reference the virtual volume segment copy in the second storage pool. Upon deletion of the point-in-time copy of the virtual volume, the virtual volume segment copy in the second storage pool may be updated with data from the point-in-time temporary virtual volume.

Abstract: A video transcoder for converting an encoded input video bit-stream having one spatial resolution into an encoded output video bit-stream having a lower spatial resolution, wherein motion-vector dispersion observed at the higher spatial resolution is quantified and used to configure the motion-vector search at the lower spatial resolution. For example, for video-frame areas characterized by relatively low motion-vector dispersion values, the motion-vector search may be performed over a relatively small vector space and with the use of fewer search patterns and/or hierarchical search levels. These constraints enable the transcoder to find appropriate motion vectors for inter-prediction coding without having to perform an exhaustive motion-vector search for these video-frame areas, which advantageously reduces the computational complexity and processor load compared to those of a comparably performing prior-art video transcoder.

Abstract: A data storage system includes at least one host device configured to initiate a data request, at least one target device configured to store data, and a serial attached SCSI (SAS) switch coupled between the at least one host device and the at least one target device. The SAS switch includes a cache memory and includes control programming configured to determine whether data of the data request is stored in the cache is at least one of data stored in the cache memory of the SAS switch or data to be written in the cache memory of the SAS switch. The cache memory of the SAS switch is a shared cache that is shared across each of the at least one host device and the at least one target device.

Abstract: A method for backing up and restoring data across multiple operating systems executed by a computing product executing computer implemented instructions, wherein each operating system includes a daemon. Embodiments may include receiving a backup initiation trigger from an initial daemon on an initial operating system. This method may include relaying the backup initiation trigger to other daemons on other operating systems. This method may also include receiving snapshot requests from the other daemons, wherein each of the snapshot requests are requests for snapshots of storage associated with an operating system of one of the other operating systems. This method may further include sending received snapshot requests from the other daemons to a storage controller.

Abstract: A signal generator circuit for reducing power consumption of out-of-band message communications between a first device including the signal generator circuit and a second device coupled to the first device comprises a switching circuit and a controller coupled to the switching circuit. The controller is operative to receive a reference clock signal and at least a first control signal indicative of a request for the first device to send a message to the second device when the first device is in a first mode of operation. The controller generates an output control signal and an output data signal. The output control signal is operative as a function of the first control signal to selectively power up the switching circuit and a transmitter driver during the first mode. The output data signal includes the message supplied to the transmitter driver for transmission to the second device during the first mode.

Abstract: Coding circuitry for difference-based data transformation in an illustrative embodiment comprises a difference-based encoder having a plurality of processing stages, with the difference-based encoder being configured to generate respective orders of difference from a sequence of data samples and to output encoded data determined based on at least a selected one of the orders of difference. The coding circuitry may be configured to implement lossless, linear compression of the sequence of data samples. The coding circuitry may additionally or alternatively comprise a difference-based decoder having a plurality of processing stages, with the difference-based decoder being configured to process encoded data comprising selected ones of a plurality of orders of difference and to reconstruct a sequence of data samples based on the selected orders of difference.

Abstract: Reframing circuitry controls communications between a physical layer device and a link layer device. In a first direction of communication, the reframing circuitry receives a container frame with the container frame having a first arrangement of columns, and outputs a virtual container frame that includes a modified version of the container frame received by the reframing circuitry, with the modified version of the container frame having a second arrangement of columns different than the first arrangement of columns. For example, the reframing circuitry in generating the modified version of the container frame may remove a path overhead column of the container frame and replace that path overhead column with a stuff column in the modified version of the container frame. The virtual container frame may be configured to include the path overhead column that was removed from the container frame in generating the modified version of the container frame.

Abstract: A charge trap type of memory having a memory channel with vertical and possibly horizontal components is described. The invention includes a new operation method of simultaneous hole and electron injection operation for high speed and high reliability non-volatile memories, as well as high-density non-volatile memories. Array implementations for high-density memory arrays and high-speed memory arrays and their fabrication methods are also described.

Abstract: A hard disk drive or other disk-based storage device comprises a storage disk, a read/write head configured to read data from and write data to the storage disk, and control circuitry coupled to the read/write head and configured to process data received from and supplied to the read/write head and to control positioning of the read/write head relative to the storage disk. The control circuitry comprises a disk controller and read channel circuitry, with the read channel circuitry comprising a read channel memory. The control circuitry is further configured to selectively permit the disk controller to access the read channel memory. For example, the disk controller may be permitted to access the read channel memory only when the read channel circuitry is not performing a read operation.

Abstract: A method includes addressing, through a command generated by an application executing on a computing platform, one or more device(s) in storage communication with the computing platform based on an appropriate communication link. The method also includes accessing, based on the addressing, a physical register of the one or more device(s) through an appropriate interface therein. Further, the method includes obtaining statistical information associated with a performance of the one or more device(s) at the computing platform through the access of the physical register.

Abstract: An interlock apparatus for a vacuum circuit breaker includes a pair of hindering units configured to allow or prevent a motion of a breaker body to an connection position or a disconnection position; a pair of first interlock bars configured to change a width of the breaker body to be greater than the predetermined spacing distance of the hindering units in a first position where the first interlock bars are spaced from each other, or to change the width of the breaker body to be smaller than the predetermined spacing distance; and a second interlock bar vertically movable to an up position and a down position, the up position for moving the first interlock bars to the first position, and the down position for returning the first interlock bars to the second position by being separated from the interposed position between the first interlock bars.

Abstract: A reference circuit comprises a first proportional to temperature component providing a first quantity exhibiting a first type of variation as a function of temperature, a first complementary to temperature component providing a second quantity exhibiting a second type of variation as a function of temperature that is complementary to the first type of variation, and curvature correction circuitry. An output of the reference circuit provides a reference signal generated based on a combination of the first and second quantities. The curvature correction circuitry is coupled to the reference circuit output and comprises at least one additional complementary to temperature component. The curvature correction circuitry adjusts the reference signal in a feedback arrangement to compensate for a temperature response bowing effect attributable to combining the first and second quantities. The reference circuit may be implemented in a disk-based storage device for use in fly height control or other control functions.

Abstract: Disclosed is a method and apparatus for pre-fetching child states in an NFA cell array. A pre-fetch depth value is determined for each transition in an NFA graph. The pre-fetch depth value is accessed for transition from an active state in the NFA graph. The child states of the active state are pre-fetched to the depth of the pre-fetch depth value recursively. A loader loads the pre-fetched states into the NFA cell array.

Abstract: An apparatus having a circuit is disclosed. The circuit may be configured to (i) generate a sequence of hash values in a table from a stream of data values with repetitive values, (ii) find two consecutive ones of the hash values in the sequence that have a common value and (iii) create a shortened hash chain by generating a pointer in the table at an intermediate location that corresponds to a second of the two consecutive hash values. The pointer generally points forward in the table to an end location that corresponds to a last of the data values in a run of the data values.