Abstract: Methods and apparatus for enabling FCS and zoning operations in an enhanced SAS expander. Features and aspects hereof provide for enhanced logic within a SAS expander to detect receipt of an SAF in a zoning capable SAS expander and to modify the SAF to correct the zone group identifier and associated CRC to enable switching among a plurality of established connection (as provided by FCS enhancement) while maintaining accurate zoning information.

Abstract: Various systems and methods for media defect detection.

Abstract: Disclosed is method of matching a character class to a symbol of an input stream. A character class, or a plurality of character classes, is defined into an accessible format which when accessed is compared to a symbol in an input stream. The format may be stored in an NFA array cell or it may be broadcast to the cell array with an input symbol for comparison.

Abstract: A depth imager such as a time of flight camera comprises a driver circuit and an optical source. The driver circuit comprises a frequency control module and a controllable oscillator having a control input coupled to an output of the frequency control module. An output of the controllable oscillator is coupled to an input of the optical source, and a driver signal provided by the driver circuit to the optical source utilizing the controllable oscillator varies in frequency under control of the frequency control module in accordance with a designated type of frequency variation, such as a ramped or stepped variation. The driver circuit may additionally or alternatively comprise an amplitude control module, such that a driver signal provided to the optical source varies in amplitude under control of the amplitude control module in accordance with a designated type of amplitude variation.

Abstract: Method and system for providing increased frequency of flash memories compatible to Serial Peripheral Interface (SPI) bus protocol by delayed data capturing so that system boot loader down load time reduces for a given memory configuration. Methods and systems are provided for operating the memory at the device rated frequency.

Abstract: Disclosed is an adaptive negative bit-line boost write assist technique in which coupling capacitance scales with the number of rows and thereby maintains a constant negative bit-line level. The change in the coupling capacitance in neighboring signals as the height increases is utilized. The change is utilized for negative bit-line voltage generation.

Abstract: An apparatus, method and system for offset compensation in a pipeline analog-to-digital converter. A group of capacitors includes one or more sampling capacitors and one or more feedback capacitors, wherein an input to the pipeline analog-to-digital converter circuit is connected to group of capacitors. An amplifier includes a non-inverting input terminal connected to a ground and an inverting input connected to the group of capacitors. The sampling and feedback capacitors are both partitioned in the same ratio to form partitioned capacitors such that a smaller of the partitioned capacitors is employed for offset compensation with respect to the pipeline analog-to-digital converter.

Abstract: Techniques are described for constructing maximum transition run (MTR) modulation code based upon a multi-level (ML) run-length limited (RLL) finite state machine (FSM) that implements different sets of penalties. A processor is configured to receive information from a hard disk drive (HDD) via a read channel and recover data from the HDD using MTR modulation code. A memory has computer executable instructions configured for execution by the processor to model a magnetic recording channel as a partial response channel, model a source of information to the magnetic recording channel to provide an optimized Markov source, and construct an MTR modulation code to mimic the optimized Markov source based upon an FSM having a limited transition run length and a multi-level periodic structure. The FSM provides at least two different sets of penalties in a period.

Abstract: Systems and methods for data processing, and more particularly to systems and methods for selectable positive feedback data processing.

Abstract: A system is described for constructing maximum transition run modulation code based upon a multi-level run-length limited finite state machine. A processor is configured to receive information from a hard disk drive via a read channel and recover data from the hard disk drive using maximum transition run modulation code. A memory has computer executable instructions configured for execution by the processor to model a magnetic recording channel as a partial response channel, model a source of information to the magnetic recording channel to provide an optimized Markov source, and construct a maximum transition run modulation code to mimic the optimized Markov source based upon a finite state machine having a limited transition run length and a multi-level periodic structure.

Abstract: Various systems and methods for media defect detection.

Abstract: A receiver has an input and a decision feedback equalizer (DFE). The DFE couples to the receiver input and has at least one tap coefficient. An input signal, having a first amplitude level insufficient to cause significant non-linear distortion in the receiver, is applied to the receiver input. After the DFE adapts to the applied input signal having the first amplitude level by adjusting the at least one tap coefficient, the adaptation process is stopped. Then the at least one tap coefficient is scaled by a factor ? and the amplitude of input signal is adjusted to a second amplitude level greater than the first amplitude level by the scale factor ?. Although the second amplitude level might be sufficient to cause significant non-linear distortion in the receiver, the scaled tap coefficient has the correct values for proper DFE operation in the presence of the non-linear distortion.

Abstract: Techniques for use in integrated circuit design systems for extracting noise threshold data for selected cells. For example, a method comprises the following steps. A cell is selected from one or more cells in a given collection of standardized cells. Each of the one or more cells represents one or more functional circuit design blocks that are usable as part of a design of an integrated circuit. A noise signal is generated or selected. The noise signal is applied to an input node of the selected cell. Noise threshold data is identified using a noise analysis module, for a given set of process, voltage and temperature variations, for an output node of the selected cell based on the noise signal applied to the input node of the selected cell.

Abstract: An improved start-up (soft-start) circuit for use with voltage regulators, and an improved regulator start-up methodology. For example, an apparatus includes a voltage regulator circuit and a start-up circuit operatively coupled to the voltage regulator circuit. The start-up circuit is configured to provide a current signal, during a start-up period, that generates a reference voltage at a reference input of the voltage regulator circuit such that the reference voltage ramps up at a rate substantially equal to a ramp-up rate of a supply voltage coupled to the start-up circuit and the voltage regulator circuit.

Abstract: A method includes executing, in each of a number of nodes of a cluster communication system, a specialized instance of an operating system privileged to control a corresponding hypervisor configured to consolidate one or more VM(s) on a system hardware. The one or more VM(s) is configured to be associated with a non-privileged operating system. The method also includes providing a cluster stack associated with the specialized instance of the operating system on the each of the number of nodes to enable communication between peers thereof in different nodes, and controlling the one or more VM(s) as a cluster resource through the cluster stack.

Abstract: A hard disk drive or other disk-based storage device comprises a storage disk, a write head configured to write data to the disk, and control circuitry coupled to the write head. The control circuitry comprises a write driver and degauss circuitry associated with the write driver. The degauss circuitry is configured to control a degauss signal waveform to be applied to the write head by the write driver, and comprises separate amplitude envelope control mechanisms for steady state and overshoot portions of the degauss signal waveform. The separate amplitude envelope control mechanisms may comprise, for example, separate steady state and overshoot controllers for controlling the amplitude envelope decay rates of the respective steady state and overshoot portions of the degauss signal waveform over the plurality of pulses.

Abstract: An apparatus for supporting multicast address learning in a network processor includes a task parameter decoder receiving the packet and determining parameters of the packet, a plurality of unlearned address counters recording a number of the packets to be multicast, a correlator determining destination addresses of the packet, a multicast replicator replicating the packet multiple times, and a task generator generating a generated packet with a bitmap and sending out the generated packet to an I/O adaptor over a task ring interface of the network processor. If the packet is unlearned, the unlearned address counter is then incremented and the unlearned packet is sent back to a special queue in the I/O adaptor over the task ring interface with an index to the bitmap for replicating by the multicast replicator, after replicating, the unlearned address counter is decremented. Methods for replicating unlearned/learned multicast packets within a network processor are included.

Abstract: Various embodiments of the present invention provide systems and methods for phase identification in data processing systems. As one example, a circuit is disclosed that includes a bank of matched filters with two or more matched filters tuned to detect patterns corresponding to a timing pattern sampled using different phases of a sample clock. In particular, the bank of matched filters includes at least a first matched filter tuned to detect a first pattern corresponding to the timing pattern sampled using a first phase of a sample clock, and a second matched filter tuned to detect a second pattern corresponding to the timing pattern sampled using a second phase of the sample clock. The circuits further include a logic circuit operable to determine whether the sample clock is closer to the first phase or the second phase based on an output of the first matched filter and an output of the second matched filter.

Abstract: A track-and-hold circuit comprises at least first and second amplifier stages, and switched capacitor circuitry coupled between the first and second amplifier stages. In a track mode of operation of the track-and-hold circuit, the switched capacitor circuitry is configured to decouple inputs of the second amplifier stage from respective outputs of the first amplifier stage and to couple the inputs of the second amplifier stage to a common mode voltage via respective first and second capacitors. In a hold mode of operation of the track-and-hold circuit, the switched capacitor circuitry is configured to couple the inputs of the second amplifier stage to the respective outputs of the first amplifier stage via the respective first and second capacitors. Multiple instances of the track-and-hold circuit may be implemented in parallel in a time-interleaved analog-to-digital converter.