Abstract: A method for reducing an amount of time required for performing consistency checking in a redundant storage system includes steps of: providing an information repository associated with each of a primary drive and at least one redundant drive; storing, in the information repository, information relating to input/output failures on the primary drive and redundant drive; determining a likelihood that one or more regions of the primary drive and/or redundant drive contains inconsistent data as a function of the information stored in the information repository; and performing consistency checking on the one or more regions of the primary drive and the redundant drive determined to have at least a prescribed likelihood of containing inconsistent data to thereby reduce the amount of time required for performing consistency checking.
Abstract: An apparatus comprising a preamplifier, a channel, and a controller. The preamplifier may be configured to read/write data to a drive with a read/write head, in response to (i) a plurality of digital control signals multiplexed to be sent/received over a first bus and (ii) one or more analog data signals sent/received over a second bus. The channel may be configured to (i) connect to the first and second bus, and (ii) send/receive the plurality of digital control signals through (a) a plurality of interconnects and (b) the first bus. The controller may be configured to send/receive the digital control signals over the interconnects. The apparatus may be configured to (i) read/write the analog data signals to the drive and (ii) generate the digital control signals, in response to one or more input/output requests received from a drive interface.
Abstract: An apparatus generally including a first circuit and a second circuit. The first circuit may be configured to (i) receive a configuration signal that identifies a current one of a plurality of communications standards and (ii) generate a plurality of matrix elements based on the configuration signal. The second circuit may include a plurality of matrixes. The second circuit may be configured to (i) fill the matrixes with the matrix elements and (ii) generate an encoded signal by forward error correction encoding an input signal using the matrixes. The encoded signal generally complies with the current communications standard.
Type:
Grant
Filed:
May 26, 2011
Date of Patent:
April 15, 2014
Assignee:
LSI Corporation
Inventors:
Pavel A. Panteleev, Elyar E. Gasanov, Ilya V. Neznanov, Andrey P. Sokolov, Yurii S. Shutkin
Abstract: A read channel is configured to receive at least part of a data fragment read from a storage media into a register, wherein the data fragment is configured to be formatted with a preamble, a sync mark (e.g., a syncMark), and user data, and wherein the data fragment is missing a sync mark. A position in the data fragment is selected, a sync mark is assumed at the selected position. The data is then processed assuming the sync mark is at the selected position of the data fragment to determine whether the data converges. When a determination is made that the data converges, the data is recovered.
Type:
Grant
Filed:
October 12, 2012
Date of Patent:
April 15, 2014
Assignee:
LSI Corporation
Inventors:
Chu N. Ying, Lei Chen, Herjen Wang, Johnson Yen
Abstract: In order to compensate for phase offset between different sets of circuitry having different synchronous clock domains, transmit (TX) circuitry of one domain is configured to transmit a pattern signal (e.g., a pseudo random bit sequence) to receive (RX) circuitry of the other domain. The RX circuitry cycles through a number of different phase-shifted RX clock signals to determine which selected clock signals result in valid RX pattern signals. The RX circuitry is then able to select one of the phase-shifted clock signals for use in normal processing of an RX data signal received from the TX circuitry.
Abstract: An apparatus, method and system for offset compensation in a pipeline analog-to-digital converter. A group of capacitors includes one or more sampling capacitors and one or more feedback capacitors, wherein an input to the pipeline analog-to-digital converter circuit is connected to group of capacitors. An amplifier includes a non-inverting input terminal connected to a ground and an inverting input connected to the group of capacitors. The sampling and feedback capacitors are both partitioned in the same ratio to form partitioned capacitors such that a smaller of the partitioned capacitors is employed for offset compensation with respect to the pipeline analog-to-digital converter.
Abstract: In one embodiment, a turbo equalizer has an LDPC decoder, a channel detector, and one or more adjustment blocks for recovering an LDPC codeword from a set of input samples. The decoder attempts to recover the codeword from an initial set of channel soft-output values and generates a set of extrinsic soft-output values, each corresponding to a bit of the codeword. If the decoder converges on a trapping set, then the channel detector performs detection on the set of input samples to generate a set of updated channel soft-output values, using the extrinsic soft-output values to improve the detection. The one or more adjustment blocks adjust at least one of (i) the extrinsic soft-output values before the channel detection and (ii) the updated channel soft-output values. Subsequent decoding is then performed on the updated and possibly-adjusted channel soft-output values to attempt to recover the codeword.
Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes an equalizer circuit and a data detection circuit. The equalizer circuit is operable to filter a series of samples based at least in part on a filter coefficient and to provide a corresponding series of filtered samples. The data detection circuit includes: a core data detector circuit and a coefficient determination circuit. The core data detector circuit is operable to perform a data detection process on the series of filtered samples and to provide a most likely path and a next most likely path. The coefficient determination circuit operable to update the filter coefficient based at least in part on the most likely path and the next most likely path.
Type:
Grant
Filed:
December 2, 2011
Date of Patent:
April 15, 2014
Assignee:
LSI Corporation
Inventors:
Haitao Xia, Weijun Tan, Nenad Miladinovic, Shaohua Yang
Abstract: A method for branch metric calculation in a plurality of communications standards is disclosed. The method generally includes steps (A) to (C). Step (A) may calculate a plurality of sum values by adding a plurality of first values related to a plurality of information bits, a plurality of second values related to the information bits and a plurality of third values related to a plurality of parity bits. Step (B) may generate a plurality of permutated values by permutating the sum values based on a configuration signal. The configuration signal generally identifies a current one of the communications standards. Step (C) may generate a plurality of branch metrics values by adding pairs of the permutated values.
Type:
Grant
Filed:
June 9, 2011
Date of Patent:
April 15, 2014
Assignee:
LSI Corporation
Inventors:
Pavel A. Panteleev, Elyar E. Gasanov, Ilya V. Neznanov, Andrey P. Sokolov, Yurii S. Shutkin
Abstract: An apparatus comprising an input circuit, a cross coupled active circuit and an output circuit. The input circuit may be configured to generate a first portion of an intermediate signal in response to an input signal. The cross coupled active circuit may be configured to generate a second portion of the intermediate signal in response to a feedback of an output signal. The output circuit may be configured to generate the output signal in response to the intermediate signal. The output signal may pass frequencies above a target frequency.
Abstract: Luminaires are disclosed that include refractive and/or reflective structures that can provide or distribute lighting for a given area with high uniformity and efficiency. The structures can be used to distribute light from one or more light sources for lighting target areas with a desired light distribution. The lighting structures can be included in light strips or luminaires. Such luminaire can be utilized in place of fluorescent lights and can facilitate quick and easy retrofit for previous fluorescent lighting applications. The disclosed techniques and systems (including components and structures) can be particularly useful when employing one or more LEDs as light sources.
Abstract: A hard disk drive or other disk-based storage device comprises a storage disk, a read/write head configured to read data from and write data to the disk, and control circuitry coupled to or otherwise associated with the read/write head. The control circuitry comprises a write driver configured to generate a write signal for data to be written to the storage disk, and a multiple-slope transition controller associated with the write driver and configured to control a data transition in the write signal such that the data transition comprises at least two different segments each having a different slope, with the transition controller comprising separate slope control mechanisms for each of the segments. By way of example, the data transition may comprise a dual-slope transition having first and second segments arranged sequentially between a start point and an end point of the data transition.
Type:
Grant
Filed:
March 9, 2012
Date of Patent:
April 15, 2014
Assignee:
LSI Corporation
Inventors:
Boris Livshitz, Jeffrey A. Gleason, Jason S. Goldberg, Paul Mazur, Cameron C. Rabe
Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having scan cells. The scan test circuitry is configured to control at least a given one of the scan cells so as to prevent the scan cell from capturing a potentially non-deterministic value from a portion of the additional circuitry. The portion of the additional circuitry that provides the potentially non-deterministic value may comprise, for example, at least one of a mixed signal logic block and a memory block of the additional circuitry. The given scan cell may be controlled by configuring the scan cell such that it is unable to capture data in a scan capture mode of operation in which it would otherwise normally be able to capture data.
Type:
Grant
Filed:
July 27, 2012
Date of Patent:
April 15, 2014
Assignee:
LSI Corporation
Inventors:
Ramesh C. Tekumalla, Prakash Krishnamoorthy
Abstract: A lighting apparatus is shown and described. In one aspect, the lighting apparatus includes a light source, a plate, and frame. The light source can include one or more lighting elements that are in thermal communication with the light source. The plate can have a dissipative portion extending outward from a point of thermal communication between the plate and the light source. The frame can at least partially enclose the light source and may also be in thermal communication therewith.
Type:
Grant
Filed:
May 6, 2013
Date of Patent:
April 15, 2014
Assignee:
LSI Industries, Inc.
Inventors:
James G. Vanden Eynden, James P. Sferra, Larry A. Akers, John D. Boyer
Abstract: A vacuum interrupter is provided. As a main shield and sub shields are installed in an overlapping manner, an equipotential distribution can be mitigated and thusly a dielectric strength can be enhanced. Also, as a curved portion is formed at each end of the shields, concentration of an electric field at an end of each shield can be prevented and accordingly an electric field value can be lowered. Consequently, the dielectric strength can be remarkably enhanced, resulting in an effective prevention of a dielectric breakdown.
Abstract: Methods and apparatus are provided for validating a detection of RRO address marks. After a potential RRO address mark is detected, a disclosed RROAM validation metric evaluates the energy of the remaining RRO data bits in the servo sector, relative to a predefined energy threshold. In addition, the number of remaining RRO data bits in the servo sector is compared to an expected value. The detected RRO address mark is validated in an exemplary embodiment if the RROAM validation metric satisfies the predefined energy threshold and the proper number of remaining RRO data bits is detected in the servo sector. The potential RRO address mark can optionally be discarded if the potential RRO address mark is not validated.
Type:
Grant
Filed:
October 26, 2011
Date of Patent:
April 15, 2014
Assignee:
LSI Corporation
Inventors:
Viswanath Annampedu, Xun Zhang, Jeffrey P. Grundvig
Abstract: Techniques are described for increasing a lifetime of a plurality of blocks of memory by equalizing a variation between the blocks. In operation, blocks to be written are allocated from a set of blocks having a lifetime factor below a threshold. The threshold is reset as required to resupply the set of blocks available for allocation.
Abstract: Disclosed is a apparatus and method for detecting a cut-off frequency of a pulse signal, the apparatus including an input processor configured to generate a second pulse signal at a time when a rising edge and a falling edge of a first pulse signal appear, in a case the first pulse signal, which is a pulse signal of a monitoring object, is inputted, a counter configured to count a clock signal relative to the second pulse signal generated by the input processor, a reset processor configured to reset the counter at every predetermined (set) period, and a detector configured to generate and output a cut-off frequency of a detection signal, in a case an output value of the counter exceeds a predetermined (set) threshold during the predetermined period.
Abstract: Systems, circuits, devices and/or methods related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing.