Abstract: A reference circuit includes an NMOS transistor, a PMOS transistor and a bias circuit. The NMOS transistor includes a source connected with a first voltage supply and a gate adapted to receive a first bias signal. The PMOS transistor includes a source connected with a second voltage supply, a gate adapted to receive a second bias signal, and a drain connected with a drain of the NMOS transistor at an output of the reference circuit. The bias circuit generates the first and second bias signals. Magnitudes the first and second bias signals are configured to control a reference signal generated by the reference circuit such that when the reference signal is near a quiescent value of the reference signal, a current in the reference circuit is below a first level, and when the reference signal is outside of the prescribed limits, the current in the reference circuit increases nonlinearly.

Abstract: An input circuit in high speed counter module for PLC is provided, the input circuit being configured such that various types of pulse signals are changed to a single type of pulse signal and transmitted to an MPU, whereby the type of input pulse is checked or an operation of checking addition/deduction is omitted to increase an interrupt process speed.

Abstract: An interface device to interface a processing device and a memory device includes an error correcting code (ECC) encoder to calculate ECC bit(s) and to provide the ECC bit(s) to the processing device based at least in part on data provided by the memory device, thereby eliminating a need to store the ECC bits in the memory device. The interface device may include a parity encoder to provide parity bit(s) to the memory device as a function of data provided by the processing device, and a parity decoder to selectively modify the ECC bit(s) as a function of the data and parity bit(s) provided by the memory device. The ECC encoder may provide ECC bits, and the parity decoder may selectively modify the ECC bits provided to the processing device based on data provided by the memory device and parity bit(s) provided by the memory device.

Abstract: In one embodiment a variable barrel shifter includes a shifter operable to apply a cyclic shift to each of a number of portions of a data word, a pivot circuit operable to swap sections of the data word around at least one pivot point in the data word, a first multiplexer operable to select between an input of the variable barrel shifter or an output of the pivot circuit as an input to the shifter, a second multiplexer operable to select between the input of the variable barrel shifter or an output of the shifter as an input to the pivot circuit, and a third multiplexer operable to select between the output of the shifter or the output of the pivot circuit as an output to the variable barrel shifter.

Abstract: A non-binary low density parity check data decoder comprises a variable node processor operable to update variable node symbol values according to a plurality of elements in a non-binary Galois Field, a check node processor connected to the variable node processor and operable to perform parity check calculations, and a controller operable to perform symbol flipping and to control decoding iterations in the variable node processor and the check node processor.

Abstract: Aspects of the disclosure pertain to a read channel system and method for providing sector prioritization for promoting improved sector processing performance. The system and method, during processing of sectors of data, prioritize each of the sectors for further processing based upon: a global iteration index of each sector, trapping set characteristics of each sector and processing latency of each sector.

Abstract: A method for electing a ring manager of ring topology network and a node are disclosed, where, to this end, a node responsible for electing the ring manager periodically requests each node of diagnostic information on packet traffic and receives the diagnostic information on packet traffic from each node, newly elects a node capable of performing a ring manager role, and informs each node of information on the newly elected ring manager, whereby, the ring network can be more effectively operated because the ring manager is elected based on network load status that changes in real time even in the course of a ring network being initially set up and operated responsive to structural conditions including hop count of each nod and MAC node.

Abstract: Clock buffers in a clock and data recovery (CDR) system are trimmed by receiving a first transmitted clock-like data pattern in a reduced rate mode, locking the CDR using the received version of the first transmitted clock-like data pattern; and receiving a second transmitted clock-like data pattern. The first transmitted clock-like data pattern is transmitted using a first rate mode and the reduced rate mode divides the first rate mode by an integer value. The second transmitted clock-like data pattern has a run-length that is an integer division of a run-length of the first transmitted clock-like data pattern. A phase of the clock buffers is adjusted using the second transmitted clock-like data pattern. The received first transmitted clock-like data pattern has edges that correspond to only positive or negative edges of the first transmitted clock-like data pattern.

Abstract: Aspects of the disclosure pertain to a system and method for providing zero gain start (ZGS) and gain acquisition based on an adaptive analog-to-digital converter (ADC) target. The adaptive ADC target is used to collect channel characteristics and based on the adaptive ADC target, an adjusted 2T amplitude target value is generated.

Abstract: An apparatus includes a first circuit and a second circuit. The first circuit may be configured to generate (i) a compressed representation of an input sequence of characters and (ii) statistics regarding one or more types of information in the compressed representation of the input sequence of characters. The second circuit may be configured to generate a compressed bitstream representation of the input sequence of characters in response to the compressed representation of the input sequence of characters and one or more of the statistics regarding the one or more types of information in the compressed representation of the input sequence of characters. The bitstream values encoding the one or more types of information are generally determined based upon a frequency of occurrence of the one or more types of information in the compressed representation of the input sequence of characters.

Abstract: systems and methods for data processing particularly related local iteration randomization in a data decoding circuit.

Abstract: An apparatus includes a first circuit and a second circuit. The first circuit may be configured to generate a reduced representation of an input sequence of characters by replacing a repetition of a sequence of one or more characters by a code representing the repetition of the sequence of one or more characters. The second circuit may be configured to generate a compressed representation of the input sequence of characters in response to the reduced representation of the input sequence of characters. The second circuit is generally configured to recognize the code representing the repetition of the sequence of one or more characters and take into account the repetition of the sequence of one or more characters during a compression operation.

Abstract: An adaptive detector, such as a maximum a posteriori (MAP) detector for a read channel, is disclosed. In one or more embodiments, a data processing apparatus, such as a read channel digital front end, includes an equalizer configured to equalize X sample data to yield equalized Y sample data. A noise predictive filter configured to receive the equalized Y sample data yielded by the equalizer is operable to filter noise in the equalized Y sample data. A detector is configured to perform iterative data detection on the filtered equalized Y sample data. The detector is operable to program a branch metric, a variance, and a scaling factor for equalizer adaptation during a global iteration of the detector.

Abstract: A memory device includes a memory array comprising multi-level memory cells, and control circuitry coupled to the memory array. The control circuitry is configured to perform accelerated soft read operations on at least a portion of the memory array. A given one of the accelerated soft read operations directed to a non-upper page of the memory array comprises at least one hard read operation directed to a corresponding upper page of the memory array. For example, the given accelerated soft read operation may comprise a sequence of multiple hard read operations including a hard read operation directed to the non-upper page and one or more hard read operations directed to the corresponding upper page.

Abstract: Systems, circuits, devices and/or methods related to systems and methods for data processing, and more particularly to systems and methods for media defect detection.

Abstract: A read channel is configured to receive at least part of a data fragment read from a storage media into a register, wherein the data fragment is configured to be formatted with a preamble, a sync mark (e.g., a syncMark), and user data, and wherein the data fragment is missing a sync mark. A position in the data fragment is selected, a sync mark is assumed at the selected position. The data is then processed assuming the sync mark is at the selected position of the data fragment to determine whether the data converges. When a determination is made that the data converges, the data is recovered.

Abstract: Disclosed is a device and method for providing a bounded bias voltage with improved Process Voltage Temperature (PVT) adjustment. An embodiment may include a bias_n generation circuit that adjusts a bias_n voltage for PVT as a function of two bias_n NMOS transistors/diodes and a bias_p generation circuit that adjusts a bias_p voltage for PVT as a function of two bias_p PMOS transistors/diodes. An embodiment may further include a PVT adjusted bounded bias voltage circuit comprised of a NMOS transistor with the bias_n voltage at the gate and a PMOS transistor with the bias_p voltage at the gate such that a common connection between the NMOS and PMOS transistors generates a bounded bias voltage adjusted for PVT as a function of two body biased voltages (bias_n/bias_p). The bounded bias voltage may be used to provide a low supply voltage to a low voltage device using an available high voltage supply.

Abstract: Scalable control/management data structures enable optimizing performance and/or attempting to achieve a particular performance target of an SSD in accordance with host interfacing, number of NVM devices, NVM characteristics and size, and NVM aging and performance decline. Pre-scaled data structures are included in SSD controller firmware loadable at system initialization. Static data structure configurations enable load-once-operate-for-product-lifetime operation for consumer applications. Dynamic configurations provide sequences of data structures pre-scaled to optimize operation as NVM ages and performance declines. Pre-configured adjustments in data structure size included in consecutive configurations periodically replace earlier configurations at least one time during product lifetime, producing a periodic rescaling of data structure size to track changes in aging NVM.

Abstract: Aspects of the disclosure pertain to a read channel system and method for providing sector prioritization for promoting improved sector processing performance. The system and method, during processing of sectors of data, prioritize each of the sectors for further processing based upon: a global iteration index of each sector, trapping set characteristics of each sector and processing latency of each sector.

Abstract: A vector processor is provided having an instruction set with a vector convolution function. The disclosed vector processor performs a convolution function between an input signal and a filter impulse response by obtaining a vector comprised of at least N1+N2-1 input samples; obtaining N2 time shifted versions of the vector (including a zero shifted version), wherein each time shifted version comprises Ni samples; and performing a weighted sum of the time shifted versions of the vector by a vector of Ni coefficients; and producing an output vector comprising one output value for each of the weighted sums. The vector processor performs the method, for example, in response to one or more vector convolution software instructions having a vector input. The vector can comprise a plurality of real or complex input samples and the filter impulse response can be expressed using a plurality of coefficients that are real or complex.