Patents Assigned to LSI
  • Publication number: 20140101501
    Abstract: An integrated circuit comprises a decoder having a plurality of select signal outputs, a multiplexer having a plurality of select signal inputs subject to a specified select signal constraint, and scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells coupled between respective ones of the select signal outputs of the decoder and respective ones of the select signal inputs of the multiplexer. The scan test circuitry is configured to control at least a given one of the scan cells so as to prevent violation of the select signal constraint in conjunction with scan testing. The multiplexer may be, for example, a one-hot multiplexer for which the select signal constraint indicates that only one of the select signal inputs should receive a logic high select signal at a particular time.
    Type: Application
    Filed: October 5, 2012
    Publication date: April 10, 2014
    Applicant: LSI Corporation
    Inventors: Narendra B. Devta Prasanna, Ramesh C. Tekumalla
  • Publication number: 20140101480
    Abstract: A storage system assigns one or more large disks in a storage enclosure as a common dedicated hot spare that is used by multiple RAID groups. Storage space equivalent to the smallest physical disk in a RAID group is allocated on the common dedicated hot spare. A mapping of this allocated storage space to the RAID group is maintained in nonvolatile memory. When a disk fails in the RAID group, the allocated storage space on the common dedicated hot spare receives a rebuild of the failed disk. Once the rebuild is complete, the allocated storage space acts as part of the RAID group. When the failed disk is replaced, the data on the allocated storage space is copied to the replacement disk. Once the copy is complete, the allocated storage space is once again set to act as a dedicated hot spare to the RAID group.
    Type: Application
    Filed: October 5, 2012
    Publication date: April 10, 2014
    Applicant: LSI CORPORATION
    Inventors: Prafull Tiwari, Sumit Verma, Madan Mohan Munireddy
  • Publication number: 20140097798
    Abstract: Disclosed herein is a battery protection circuit module device. The battery protection circuit module device includes a charging unit, a battery protection circuit module, and a system. The charging unit includes first and second MOSFET switches, and supplies externally input power to a battery or a system. The battery protection circuit module includes the battery, third and fourth MOSFET switches configured to be selectively turned on and off, a resistor and a capacitor configured to supply the voltage of the battery to the PCM controller as driving power, and the PCM controller configured to control the third and fourth MOSFET switches. The system is operated using the voltage of the battery or externally input voltage. The third and fourth MOSFET switches of the battery protection circuit module are connected via a common drain structure and a common drain terminal is connected to an internal ground.
    Type: Application
    Filed: December 5, 2012
    Publication date: April 10, 2014
    Applicant: KOREA LSI CO.,LTD
    Inventor: Su Jung HAN
  • Publication number: 20140101379
    Abstract: Dynamically varying Over-Provisioning (OP) enables improvements in lifetime, reliability, and/or performance of a Solid-State Disk (SSD) and/or a flash memory therein. A host coupled to the SSD writes newer data to the SSD. If the newer host data is less random than older host data, then entropy of host data on the SSD decreases. In response, an SSD controller of the SSD dynamically alters allocations of the flash memory, decreasing host allocation and increasing OP allocation. If the newer host data is more random, then the SSD controller dynamically increases the host allocation and decreases the OP allocation. The SSD controller dynamically allocates the OP allocation between host OP and system OP proportionally in accordance with a ratio of bandwidths of host and system data writes to the flash memory.
    Type: Application
    Filed: April 22, 2012
    Publication date: April 10, 2014
    Applicant: LSI CORPORATION
    Inventor: Andrew John Tomlin
  • Publication number: 20140101185
    Abstract: In a hardware engine, finding rule matches within an input stream by executing a Nondeterministic Finite Automaton (NFA) with active states tracked in parallel cells, a Start Pointer (SP) is captured by the cell beginning a match and passed from cell to cell until the match completes, when it is reported by the cell ending the match. For multiple overlapping matches, different cells may hold different SPs, and a cell representing multiple NFA states may hold multiple SPs. Methods are given to select one SP when multiple SPs collide in the same state.
    Type: Application
    Filed: October 5, 2012
    Publication date: April 10, 2014
    Applicant: LSI CORPORATION
    Inventor: Michael Ruehle
  • Publication number: 20140100704
    Abstract: A cloud service system and method for a power system are provided. The cloud service system includes: at least one power system; a remote control server configured to receive collected data from the power system and generate and transmit a control signal to the power system; and a cloud server configured to connect the at least one power system to the remote control server through the Internet, store the collected data from the at least one power system, and provide the stored data according to a request from an external terminal.
    Type: Application
    Filed: September 25, 2013
    Publication date: April 10, 2014
    Applicant: LSIS CO., LTD.
    Inventors: Won Seok CHOI, Jong Ho PARK, Yong Hark SHIN, Jin LEE
  • Publication number: 20140101176
    Abstract: Disclosed is a method for simultaneously finding matches for rules that require greedy matching and comprehensive matching by executing a single Deterministic Finite Automaton (DFA). DFAs annotations are used to enable a single DFA to represent rules that require greedy and comprehensive matching. DFA descents are performed from various positions in an input stream, match information is recorded and match results are selectively generated (filtered) to achieve the greedy or comprehensive match behavior required by individual rules.
    Type: Application
    Filed: October 5, 2012
    Publication date: April 10, 2014
    Applicant: LSI CORPORATION
    Inventor: Michael Ruehle
  • Publication number: 20140101500
    Abstract: Circuits and methods are provided for debugging an integrated circuit. An integrated circuit includes core circuitry, scan test circuitry, scan control circuitry, and debug control circuitry. The scan test circuitry includes scan chains with scan cells interspersed throughout the core circuitry. The scan control circuitry controls the scan test circuitry to scan test the core circuitry. The debug control circuitry utilizes the scan test circuitry and controls the scan control circuitry to debug failure conditions of the integrated circuit during normal use. The scan control circuitry applies a debug clock signal to a clock port of each scan cell of a given scan chain to store data values that are generated by the core circuitry into the scan cells. The scan control circuitry controls the scan test circuitry to scan shift out the stored data values generated by the core circuitry during the debug process.
    Type: Application
    Filed: October 5, 2012
    Publication date: April 10, 2014
    Applicant: LSI Corporation
    Inventors: Sachin Shivanand Bastimane, Komal N. Shah, Ramesh C. Tekumall, Allentown Madhani
  • Publication number: 20140098844
    Abstract: Embodiments of the present invention allow for adjustment of transmitter amplitude during joint transmitter (TX) and receiver (RX) equalization. During joint TX and RX adaptation, when the receiver requires a gain update, the receiver gain update is masked above or below a preset range. The RX gain update (instruction) is encoded into a transmitter amplitude update (instruction) transferred through back channel communication. The translation of RX gain to TX amplitude update is performed after the RX gain reaches a specified range. Such masking, encoding and translation reserves a certain amount RX gain range to account for RX gain variation due to process, voltage, and temperature (PVT) changes over time, and also to offer better linear equalization in the receiver over a constrained VGA bandwidth.
    Type: Application
    Filed: October 9, 2012
    Publication date: April 10, 2014
    Applicant: LSI Corporation
    Inventors: Mohammad Mobin, Vladimir Sindalovsky, Amaresh Malipatil, Thomas F. Gibbons, JR., Ye Liu, Lane A. Smith
  • Publication number: 20140101510
    Abstract: The present inventions are related to systems and methods for decoding data in an LDPC layer decoder for LDPC codes with overlapped circulants.
    Type: Application
    Filed: October 5, 2012
    Publication date: April 10, 2014
    Applicant: LSI CORPORATION
    Inventors: Chung-Li Wang, Dan Liu, Qi Zuo, Zongwang Li, Shaohua Yang
  • Publication number: 20140101505
    Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a scan chain having a plurality of scan cells. The integrated circuit further comprises a clock distribution network configured to provide clock signals to respective portions of the integrated circuit. The clock distribution network comprises a clock tree having clock signal lines, and clock control elements arranged in respective selected ones of the clock signal lines of the clock tree, where the clock control elements are configured to separate at least one synchronous clock domain into multiple asynchronous clock domains during scan testing. The clock control elements may be configured to reduce a number of timing exceptions produced during scan testing relative to a number of timing exceptions that would otherwise be produced if scan testing were performed using the synchronous clock domain.
    Type: Application
    Filed: October 5, 2012
    Publication date: April 10, 2014
    Applicant: LSI Corporation
    Inventors: Ramesh C. Tekumalla, Prakash Krishnamoorthy, Vijay Sharma
  • Publication number: 20140101509
    Abstract: Systems, circuits, devices and/or methods related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing.
    Type: Application
    Filed: October 4, 2012
    Publication date: April 10, 2014
    Applicant: LSI Corporation
    Inventors: Shaohua Yang, Fan Zhang, Jun Xiao
  • Patent number: 8694847
    Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data set quality determination.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: April 8, 2014
    Assignee: LSI Corporation
    Inventors: Fan Zhang, Yang Han, Xuebin Wu, Shaohua Yang
  • Patent number: 8693125
    Abstract: A clock phase measurement circuit comprises a selector circuit operable to inject one of a first analog clock signal or a second analog clock signal into a signal path configured to carry an analog data signal, so that the injected analog clock signal replaces the data signal. An Analog to Digital Converter (ADC) converts the injected analog clock signal to a digital clock signal. A counter selects a time, using the second analog clock signal, to determine at least one of a phase or a magnitude of the digital clock signal. A measurement circuit determines at least one of the phase or the magnitude of the digital clock signal for at least one frequency at the selected time.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: April 8, 2014
    Assignee: LSI Corporation
    Inventor: Jeffrey P. Grundvig
  • Patent number: 8693264
    Abstract: A memory device includes a memory array comprising a plurality of memory cells arranged in rows and columns, and sensing circuitry coupled to bitlines associated with respective columns of the memory cells of the memory array. The sensing circuitry comprises, for at least a given one of the bitlines of the memory array, a sense amplifier configured to sense data on the given bitline, with the sense amplifier having at least one internal node and at least one output node. The sensing circuitry further comprises a latch circuit having a data input coupled to the output node and a control input coupled to the internal node, with the latch circuit being configured to latch sensed data from the output node responsive to a signal at the internal node.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: April 8, 2014
    Assignee: LSI Corporation
    Inventor: Md Rahim Chand Sk
  • Patent number: 8693126
    Abstract: An apparatus comprising a magnetic media and a read/write unit. The magnetic media may be configured to store data. The magnetic media may also be rotated during access of the magnetic media. The read/write unit may comprise a plurality of transducers arranged in a linear array. Each of the transducers may be fabricated on a semiconductor substrate with fixed head positions with respect to the magnetic media. The read/write unit may also be positioned in close proximity to and across the surface of the magnetic media. Each transducer may be configured to read data from the magnetic media and write data to the magnetic media.
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: April 8, 2014
    Assignee: LSI Corporation
    Inventors: Wayne L. Buckholdt, Robert W. Warren
  • Patent number: 8693120
    Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a read circuit and a combining circuit. The read circuit is operable to provide a first instance of a user data set, a second instance of the user data set, and a third instance of the user data set. The combining circuit is operable to: combine at least a first segment of the first instance of the user data set with a first segment of the second instance of the user data set to yield a first combined data segment; provide a second combined data set that includes a combination of one or more second segments from the second instance of the user data set and the third instance of the user data set; and provide an aggregate data set including at least the first combined data set and the second combined data set. The second combined data set does not incorporate a second segment of the first instance of the user data set.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: April 8, 2014
    Assignee: LSI Corporation
    Inventors: Shaohua Yang, Changyou Xu, Wu Chang, Ming Jin
  • Patent number: 8694937
    Abstract: A method of manufacturing an electronic circuit employing a flexible ramptime limit and an electronic circuit are disclosed. In one embodiment, the method includes: (1) physically synthesizing a logical representation of an electronic circuit employing flexible ramptime limits, (2) performing a timing test on the physically synthesized electronic circuit employing the flexible ramptime limits and a processor and (3) determining if there is a violation of the flexible ramptime limits.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: April 8, 2014
    Assignee: LSI Corporation
    Inventors: Alexander Tetelbaum, Rich Laubhan, Joseph Jamann, Bruce Zahn
  • Patent number: 8693121
    Abstract: A method includes designating a first sampling phase for a signal captured from a magnetic storage medium, where the signal is representative of information stored by the magnetic storage medium. The method further includes capturing a first waveform associated with the signal at the first sampling phase. The method also includes designating a second sampling phase different from the first sampling phase for the signal. The method further includes capturing a second waveform associated with the signal at the second sampling phase. The method also includes interleaving the first waveform and the second waveform to form an oversampled waveform. The first waveform and the second waveform are captured at a rate at least substantially equal to a rate at which the information stored by the magnetic storage medium was written to the magnetic storage medium.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: April 8, 2014
    Assignee: LSI Corporation
    Inventors: Bruce W. McNeill, Jason D. Byrne
  • Patent number: 8693119
    Abstract: Described embodiments cancel inter-track interference (ITI) from one or more sectors read from a desired track of a storage medium. A read channel reads one or more sectors in the desired track and generates one or more groups of sample values corresponding to each of the sectors. An ITI canceller estimates an ITI response and an ITI signal for each sample value corresponding to (i) a next adjacent track and (ii) a previous adjacent track. If the estimated ITI response of the previous adjacent track reaches a predetermined threshold, the ITI canceller subtracts the estimated ITI signal corresponding to the previous adjacent track from each associated sample value of the desired track. If the estimated ITI response of the next adjacent track reaches a predetermined threshold, the ITI canceller subtracts the estimated ITI signal corresponding to the next adjacent track from each associated sample value of the desired track.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: April 8, 2014
    Assignee: LSI Corporation
    Inventors: George Mathew, Erich Franz Haratsch, Jongseung Park, Timothy B. Lund