Abstract: In one embodiment, a bootstrap switch circuit has (i) a switch device that selectively provides a input signal as an output signal and bootstrap circuitry that provides a relatively high-voltage control signal to the gate of the switch device to turn on the switch device while preventing any over-voltage conditions from being applied to the switch device. The bootstrap circuitry includes a capacitor and a number of transistors configured as either switches or inverters. The circuit has two operating phases: one in which the capacitor gets charged while the switch device is turned off and the other in which the charged capacitor is isolated and used to generate the high-voltage control signal to be a fixed voltage difference above the current voltage level of the input signal applied to the switch device, thereby preventing an over-voltage condition.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a combination data decoder circuit. The combination data decoder circuit includes a first decoder circuit and a second decoder circuit. The first decoder circuit is operable to apply a first data decode algorithm to a decoder input to yield a decoded output. The second decoder circuit is operable to apply a second data decode algorithm to a subset of the decoded output to modify at least one element of the decoded output to yield a modified decoded output.

Abstract: Several methods and a system to implement an efficient power supply management are disclosed. In one embodiment, an apparatus of a voltage supply includes a power supply providing a voltage. The apparatus includes an active supply module communicating with a supply voltage to a voltage bus through an ORing element. The apparatus also includes a redundant supply module providing an additional voltage to the voltage bus if the active supply module fails, through an additional ORing element. The redundant supply module may be coupled with the power supply in parallel with the active supply module. Further, the apparatus includes an automatic changeover module detecting a failure of the active supply module disabling the active supply module and enabling the redundant supply module to supply the additional voltage supply to the voltage bus. Further, the apparatus also includes a voltage bus coupled with a load.

Abstract: An apparatus comprises digitally controlled oscillator circuitry, feedback circuitry operatively coupled to the digitally controlled oscillator circuitry, and comparison circuitry operatively coupled to the digitally controlled oscillator circuitry and the feedback circuitry. The feedback circuitry, in response to a clock signal generated by the digitally controlled oscillator circuitry, generates a first digital value representing a detected phase of the clock signal for a given clock signal cycle. The comparison circuitry, in response to the first digital value and to a second digital value representing a reference phase, generates a phase error value. The phase error value is useable to generate a first digital control word provided to the digitally controlled oscillator circuitry for controlling a frequency associated with the clock signal.

Abstract: The present invention relates to a vacuum interrupter in a vacuum circuit breaker. According to the present invention, there is provided an attraction member made of a ferromagnetic body for surrounding between the stationary electrode and movable electrode to attract a radial magnetic field generated in a radial direction between the stationary electrode and movable electrode by means of the attraction member, and through this a component of the radial magnetic field may be increased in an overall horizontal direction between the stationary electrode and movable electrode, and as a result the radial magnetic field may be further enhanced between both electrodes, thereby strengthening an arc driving force.

Abstract: In order to provide a solution for performing priority arbitration, a mask and reset-mask are generated in concert with a priority arbitration scheme. A plurality of requestors may issue requests for a shared resource. The priority arbitration scheme may grant access to a single requestor for a single priority assignment period. The mask may assist the priority arbitration scheme to assign priority to the plurality of requestors by temporarily removing a subset of the plurality of requestors for a particular priority assignment period. If the mask allows for no allowable requestors during the priority assignment period, a reset-mask scheme is implemented to reset the mask to permit an increased number of requestors access to the priority arbitration scheme.

Abstract: Described embodiments provide a server for transferring data packets of streaming data sessions between devices. A redundant array of inexpensive disks (RAID) array having one or more stripe sector units (SSU) stores media files corresponding to the one or more data sessions. The RAID control module receives a request to perform the write operation to the RAID array beginning at a starting data storage address (DSA) and pads the data of the write operation if the amount of data is less than a full SSU of data, such that the padded data of the write operation is a full SSU of data. The RAID control module stores the full SSU of data beginning at a starting data storage address (DSA) that is aligned with a second SSU boundary, without performing a read-modify-write operation.

Abstract: Systems and methods for out of order memory management.

Abstract: A system for, and method of, generating block timing constraints and a timing model. In one embodiment, the system includes a hierarchical modeling tool configured to: (1) generate a model file, (2) receive at least one abstracted view margin, at least one timing environment margin and at least one operational margin for inclusion in the model file, (3) generate block implementation timing constraints employing the at least one timing environment margin and the at least one operational margin and (4) generate a block timing model employing the at least one abstracted view margin and the at least one operational margin.

Abstract: An expander device and method for transmitting serial input/output (SIO) data between an initiator device and a plurality of target devices. The expander device includes a processor/controller configured to receive a master data stream from an initiator device and to transmit a returning master data stream to the initiator device. The expander device includes a plurality of target master ports coupled to the processor/controller and configured to transmit split data streams to corresponding target devices coupled thereto and to receive returning split data streams from the target devices. The processor/controller splits the master data stream, based on its data, into a plurality of split data streams, and directs the split data streams to the target master ports based on the data in the split data streams. The processor/controller also assembles a plurality of returning split data streams into the returning master data stream and transmits the returning master data stream to the initiator device.

Abstract: A differential line driver with N-paralleled slices for driving an impedance-matched transmission line. Each driver slice is a modified H-bridge driver using low-voltage, high-speed transistors. By using a voltage-dropping first resistor in each slice, a high-voltage power supply that would normally damage the transistors can be used to power the driver and produce a differential output signal with peak-to-peak amplitudes that otherwise might not be possible. Each transistor in each driver slice has a resistor disposed between the transistor and the respective output node of the driver to enhance ESD protection of the transistors and, in combination with the first resistor, to impedance match the driver to the transmission line.

Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a scan chain having a plurality of scan cells. The integrated circuit further comprises a clock distribution network configured to provide clock signals to respective portions of the integrated circuit. The clock distribution network comprises clock gating circuitry configured to control delivery of one or more of the clock signals along respective clock signal lines of the clock distribution network at least in part responsive to a scan shift control signal that is also utilized to cause the scan cells to form a serial shift register during scan testing. The clock gating circuitry may be used to determine whether a clock delay defect that causes a scan error during scan testing will also cause a functional error during functional operation, thereby improving yield in integrated circuit manufacturing.

Abstract: A RAID data storage system incorporates permanently empty blocks into each stripe, distributed among all the data storage devices, to accelerate rebuild time by reducing the number of blocks that need to be rebuilt in the event of a failure.

Abstract: An apparatus for providing a data integrity field implementation in a data processing system includes a controller operative to interface between a host device and a destination device in the data processing system for transferring at least one data block therebetween. The data processing system further includes an error detection module associated with the controller. The error detection module is operative to determine a probability of an error occurrence based at least in part on a measured current error rate for the data processing system. The controller is operative to implement an error correction methodology which is selectively adaptable as a function of the probability of an error occurrence.

Abstract: Processing input/output requests may include: processing one or more input/output (IO) requests in a first IO queue associated with a first device group; detecting a queuing of one or more IO requests in a second IO queue associated with a second device group; pausing the processing one or more input/output (IO) requests in a first IO queue associated with a first device group upon a detection of a queuing of one or more IO requests in a second IO queue associated with a second device group; processing the one or more IO requests in a second IO queue associated with a second device group; and resuming the processing one or more input/output (IO) requests in a first IO queue associated with a first device group upon a completion of the processing the one or more IO requests in a second IO queue associated with a second device group.

Abstract: A memory device includes a memory array comprising a plurality of memory cells arranged in rows and columns, and sensing circuitry coupled to bitlines associated with respective columns of the memory cells of the memory array. The sensing circuitry comprises, for at least a given one of the bitlines of the memory array, a sense amplifier configured to sense data on the given bitline, with the sense amplifier having at least one internal node and at least one output node. The sensing circuitry further comprises a latch circuit having a data input coupled to the output node and a control input coupled to the internal node, with the latch circuit being configured to latch sensed data from the output node responsive to a signal at the internal node.

Abstract: Disclosed are an apparatus for correcting an error of acquired data and a method thereof. The method includes determining whether states of at least one circuit breaker and at least one disconnecting switch included in at least one station are consistent with each other based on data received from at least one remote control apparatus including the at least one station; assigning a weight to a corresponding circuit breaker and a corresponding disconnecting switch and the station including the corresponding circuit breaker and the corresponding disconnecting switch when the determination result represents that the states of the circuit breaker and the disconnecting switch are inconsistent with each other; creating alarm information notifying a malfunction of the corresponding circuit breaker and the corresponding disconnecting switch when an accumulated weight value is equal to or greater than a preset reference weight value; and outputting an alarm corresponding to the alarm information.

Abstract: A multiple-port memory device having at least first and second ports each configured to support read and write operations. The multiple-port memory device further comprises a single-port memory device and control circuitry coupled between the first and second ports and the single-port memory device. The control circuitry is configured to multiplex input signals received over the first and second ports of the multiple-port memory device into respective input time slots of the single port of the single-port memory device, and to demultiplex output time slots of the single port of the single-port memory device into output signals that are supplied over the first and second ports of the multiple-port memory device.

Abstract: A digital modulation system provides enhanced multipath performance by using modified orthogonal codes with reduced autocorrelation sidelobes while maintaining the cross-correlation properties of the modified codes. For example, the modified orthogonal codes can reduce the autocorrelation level so as not to exceed one-half the length of the modified orthogonal code. In certain embodiments, an M-ary orthogonal keying (MOK) system is used which modifies orthogonal Walsh codes using a complementary code to improve the auto-correlation properties of the Walsh codes, thereby enhancing the multipath performance of the MOK system while maintaining the orthogonality and low cross-correlation characteristics of the Walsh codes.

Abstract: An adaptive filter configured to use multiple algorithm species that differ in the quality of echo suppression and respective burdens imposed on the computational resources of the host communication device. Depending on the available computational budget, the adaptive filter selects an algorithm species that, while supporting a relatively high quality of echo suppression, involves a relatively low risk of overwhelming the computational resources. The adaptive filter monitors changes in the available computational budget and, if appropriate or necessary, can change the algorithm species to maintain a quality of echo suppression that is optimal for the current computational budget. If a change of the algorithm species is initiated, then at least a portion of internal algorithm data from the previously running algorithm species might be transferred for use in the subsequent algorithm species.