Abstract: A base station of a wireless system comprises a local clock source and timing circuitry coupled to the local clock source. The timing circuitry is configured to adjust at least one parameter of the local clock source based at least in part on timing information extracted from designated portions of each of one or more frames of a synchronous transport signal received in the base station. The base station may further comprise a physical layer device, such as a mapper, configured to extract the timing information from the designated portions of each of the one or more frames of the synchronous transport signal. The designated portions of the one or more frames of the synchronous transport signal from which the timing information is extracted may comprise designated overhead bytes of the one or more frames, such as, for example, transport overhead (TOH) bytes.

Abstract: A low-density parity check min-sum decoder including a variable node processing unit having N+1 inputs. A first bank of N+1 two-input adders each have an associated output, and at least one of the N+1 inputs go to more than two of the adders of the first bank. A second bank of N two-input adders has no adders in common with the first bank. At least one of the adders of the first bank provides its associated output to more than one adder of the second bank. The banks of adders are disposed in series. A sign module outputs a sign value produced from one of the inputs and an output from one of the adders of the second bank. N+1 outputs are provided, where one of the outputs is the sign value.

Abstract: A method for load control in a load control device is disclosed. According to the method for load control of the present invention, a user intuitively recognizes the economic gain of a load control command in order to consider the efficiency of the load control system.

Abstract: Methods and structure for rapid offloading of cached data in a volatile cache memory of a storage controller to a nonvolatile memory. Features and aspects hereof provide an enhanced storage controller having a volatile cache memory and multiple communication channels each coupled with a corresponding nonvolatile memory device. Responsive to detecting an impending loss of power, control logic of the controller copies data from the volatile cache memory to the multiple nonvolatile memories using the multiple communication channels operating substantially in parallel. Using multiple parallel channels and nonvolatile memory substantially temporally overlapping their operations assures that the cached data can be saved to nonvolatile memory before the controller is inoperable due to power loss. A simple “file system” and error detection and correction codes on the nonvolatile memory help assure that the saved data is valid for return to the volatile memory when power is restored to the controller.

Abstract: Disclosed is a method of reliably operating a RAID storage system. A first block of data is striped across a plurality of drives following a CRUSH algorithm. The first block of data is again striped across a second plurality of drives to a D?+P? stripe and placed on free drive space following the CRUSH algorithm. The data is written in an asynchronous fashion and possibly at a time when system utilization is low.

Abstract: A method of designing a model of an integrated circuit block, an electronic design automation tool and a non-transitory computer-readable medium are disclosed herein. In one embodiment, the method includes: (1) generating an input and output timing budget for the block based on design constraints of the block and a netlist of the block, (2) updating the input and output timing budget with clock customization data based on designer knowledge of the integrated circuit and (3) providing the model for the block based on the update of the input and output timing budget, wherein the model represents clock information of the block separately from data path information of the block.

Abstract: A Solid-State Disk (SSD) controller enables dynamic higher-level redundancy mode management with independent silicon elements to provide graceful degradation as non-volatile (e.g. flash) memory elements fail during operation of an SSD implemented by the controller. Higher-level error correction provides correction of lower-level uncorrectable errors. If a failure of one of the non-volatile memory elements is detected, then the higher-level error correction is dynamically transitioned from operating in a current mode to operating in a new mode. The transition includes one or more of reducing free space available on the SSD, rearranging data storage of the SSD, recovering/storing failed user data (if possible), and determining/storing revised higher-level error correction information. Operation then continues in the new mode. If another failure of the non-volatile memory elements is detected, then another transition is made to another new mode.

Abstract: A transceiver comprises a transmitter and a receiver. At least one of the transmitter and the receiver comprises an adaptive filer. One or more coefficients of the adaptive filter are determined based at least in part on an output of a real time clock. The adaptive filter may comprise a coefficient update engine and a memory for storing a plurality of sets of adaptive filter coefficients in association with respective time indicators derived from the output of the real time clock, with the coefficient update engine being configured to determine a particular one of the sets of filter coefficients for use by the adaptive filter based at least in part on at least a subset of the time indicators. The time indicators may comprise respective time stamps generated based on the output of the real time clock at respective times at which the corresponding sets of coefficients are determined.

Abstract: A SAS expander configured to operate as a SAS expander hub receives IO requests from connected SAS expanders and relays the IO requests to SAS expanders connected to data storage devices capable of servicing such IO requests.

Abstract: Various embodiments of the present invention provide systems and methods for data processing that includes selectively reporting results out of order or in order.

Abstract: A solar power inverter having a sealing means includes: a main case having an opening on a front surface thereof, the opening open and closed by a main cover; an auxiliary case coupled to one side surface of the main case, and having an opening on a front surface thereof, the opening open and closed by an auxiliary cover; and a gasket interposed between the main case and the auxiliary case, wherein the main case and the auxiliary case are coupled to each other by coupling bolts which pass through the main case, the gasket and the auxiliary case.

Abstract: Disclosed is a hardware protocol stack, where header information of analysis-subjected protocol is stored in a register unit, comparison is made whether information recorded in the header of inputted frame mutually matches header information stored in the register unit, and data is extracted as a result of the comparison.

Abstract: A lighting apparatus is shown and described. In one aspect, the lighting apparatus includes a light source, a plate, and frame. The light source can include one or more lighting elements that are in thermal communication with the light source. The plate can have a dissipative portion extending outward from a point of thermal communication between the plate and the light source. The frame can at least partially enclose the light source and may also be in thermal communication therewith.

Abstract: A circuit for use with a memory storage device including a magnetic storage medium and a write head operative to subject the magnetic storage medium to a magnetic field in response to an application of current to the write head, includes a write circuit operative to generate a write current supplied to the write head. The write current is characterized by a current waveform that reverses polarity in accordance with data to be stored on the magnetic medium. The circuit for use with the memory storage device further includes a degauss circuit operative to generate a degaussing current supplied to the write head. The degaussing current is characterized by a current waveform that oscillates between opposite polarities with an amplitude and a frequency that change over time.

Abstract: A system having an entropy module, a memory module and a main module is disclosed. The entropy module may be configured to generate a plurality of first random numbers. The memory module may be configured to buffer (i) the first random numbers and (ii) a plurality of second random numbers. The main module is generally configured to (i) control a first transfer of the first random numbers from the entropy module to the memory module, (ii) control a second transfer of the first random numbers from the memory module to the main module, (iii) generate the second random numbers by encrypting the first random numbers and (iv) control a third transfer of the second random numbers from the main module to the memory module. The generation of the first random numbers and the generation of the second random numbers may be performed in parallel.

Abstract: In described embodiments, a variety of down-sampling techniques are employed to generate a more constrained set of floating-tap positions when compared to floating-tap Decision Feedback Equalization (DFE) architectures that allow unconstrained 1T resolution or separated floating-tap positions. Down-sampling is employed to constrain the floating-tap positions rather than positions occurring with 1T resolution or spacing. Two broad down-sampling techniques, phase pruning and phase amalgamation, are applied to a variety of exemplary DFE implementations. Although the tap positions are more constrained, the architectures select floating-tap positions containing dominant reflection inter-symbol interference (ISI) terms.

Abstract: Described embodiments provide a delay cell for a complementary metal oxide semiconductor integrated circuit. The delay cell includes a delay stage to provide an output signal having a programmable delay. The delay cell has a selectable delay value from a plurality of delay values and a selectable output skew value from a plurality of output skew values, where the cell size and terminal layout of the delay cell are uniform for the plurality of delay values and the plurality of output skew values. The delay stage includes M parallel-coupled inverter stages of stacked PMOS transistors and stacked NMOS transistors. The stacked transistors have configurable source-drain connections between a drain and a source of each transistor, wherein the selectable delay value corresponds to a configuration of the configurable source-drain connections to adjust a delay value of each of the M inverter stages and an output skew value of the delay cell.

Abstract: Systems and methods are provided for automatically configuring ports of devices within an SAS network domain. A domain control element, such as an SAS initiator, is coupled to a plurality of expander devices. The domain control element configures ports of the expander devices by traversing port connections between the expander devices to determine routing attributes of the ports. The domain control element automatically configures the ports to operate according to the routing attributes. In one aspect hereof, an initiator device of the SAS network domain serves as a control element to perform the automated configuration of routing attributes. In another aspect hereof, an expander device serves as a control element to configure routing attributes of the ports.

Abstract: Described embodiments provide a packet classifier of a network processor having a plurality of processing modules. A scheduler generates a thread of contexts for each tasks generated by the network processor corresponding to each received packet. The thread corresponds to an order of instructions applied to the corresponding packet. A multi-thread instruction engine processes the threads of instructions. A function bus interface inspects instructions received from the multi-thread instruction engine for one or more exception conditions. If the function bus interface detects an exception, the function bus interface reports the exception to the scheduler and the multi-thread instruction engine. The scheduler reschedules the thread corresponding to the instruction having the exception for processing in the multi-thread instruction engine. Otherwise, the function bus interface provides the instruction to a corresponding destination processing module of the network processor.

Abstract: Methods of designing an IC and a hierarchical design flow generator are disclosed. In one embodiment, the method includes: (1) receiving timing and physical constraints for an IC design at an apparatus, (2) establishing a hierarchical design flow for providing an implementation of the IC design employing the apparatus and (3) partitioning the hierarchical design flow into a late design flow portion and an early design flow portion employing the apparatus, wherein the late design flow portion is substantially the same for different design flow methodologies.