Abstract: A system having a memory and a processor is disclosed. The memory may be arranged as (i) a first pipeline to buffer a plurality of full resolution fields and (ii) a second pipeline to buffer a plurality of low resolution fields. The processor is generally configured to (i) receive a particular one or more of the full resolution fields and a particular one or more of the low resolution fields from the memory and (ii) generate a film mode signal based on the particular low resolution fields, the film mode signal indicating a current mode among a plurality of pull-down modes related to a current field being deinterlaced.

Abstract: A design process optimization system and method for designing a circuit, which may be an integrated circuit (IC) employing adaptive voltage and scaling optimization (AVSO). In one embodiment, the system includes: (1) a process-voltage-temperature (PVT) libraries database configured to contain PVT libraries of PVT characterizations of devices of cells from which the circuit is to be constructed and (2) a PVT library selector coupled to the PVT libraries database and configured to receive a selection indicating a supplemental objective and respond to the selection by selecting one of the PVT libraries from the PVT libraries database, a timing signoff tool later employing at most two corners from the one of the PVT libraries to perform a timing signoff with respect to the circuit.

Abstract: Described embodiments provide a hash processor for a system having multiple processing modules and a shared memory. The hash processor includes a descriptor table with N entries, each entry corresponding to a hash table of the hash processor. A direct mapped table in the shared memory includes at least one memory block including N hash buckets. The direct mapped table includes a predetermined number of hash buckets for each hash table. Each hash bucket includes one or more hash key and value pairs, and a link value. Memory blocks in the shared memory include dynamic hash buckets available for allocation to a hash table. A dynamic hash bucket is allocated to a hash table when the hash buckets in the direct mapped table are filled beyond a threshold. The link value in the hash bucket is set to the address of the dynamic hash bucket allocated to the hash table.

Abstract: One embodiment is a method for installing a virtual storage appliance on a host server platform. One such method comprises: providing an installation package to a host server platform, the installation package comprising an installation script for installing an I/O virtual machine (IOVM), an IOVM boot console, and an IOVM management module; running the installation script to create a hidden boot partition on a boot disk and copy the IOVM boot console and the IOVM management module to the hidden boot partition; rebooting the host server platform; loading the IOVM boot console and the IOVM management module from the hidden boot partition; configuring a disk array via the IOVM management module; for each disk in the array, creating a hidden boot partition and replicating the IOVM boot console and the IOVM management module; and installing a virtual storage environment using the IOVM boot console as a storage driver.

Abstract: A system generally including a clock structure analysis tool, a static timing analysis tool and a waveform tool is disclosed. The clock structure analysis tool may be configured to generate a simplified clock structure for a clock signal in a complex clock structure in a design of a circuit. The static timing analysis tool may be configured to generate a plurality of results for a plurality of intermediate signals in the simplified clock structure in response to a static timing analysis of the design. The waveform tool may be configured to generate a first representation in a graphical user interface format of the intermediate signals and the results.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a noise injection circuit. The noise injection circuit is operable to: determine a difference between a first data output and a second data output to yield an error; and augment an interim data with a noise value corresponding to the error to yield a noise injected output. The interim data may be either the first data output or the second data output.

Abstract: An apparatus and method to characterize a new process using an improved delay calculation. Multiple derating factors are used for different STA sign off corners that have a base corner with two pairs of off-corners. The approach of the present invention does not add any extra work in cell library characterization, while in the mean it increases the accuracy of the delay calculation and the library generation at corners other than standard corners.

Abstract: A system and method for reducing overall connection latencies in a SAS expander is disclosed. The SAS expander includes a plurality of ports and a route lookup table configured for providing a central resource for routing information for the ports. The SAS expander also includes a plurality of connection history caches (CHCs) associated with the ports, each CHC is configured for storing at least one successfully established connection record. Upon receiving a connection request at a particular port, that particular port may determine whether a matching connection record for the connection request is stored in its corresponding CHC. If the matching connection record is stored in its corresponding CHC, a connection may be established in response to the connection request based on the matching connection record. However, if no matching connection record is found in its corresponding CHC, the connection may be established utilizing the route lookup table.

Abstract: Amplifier architectures are provided for current sensing applications. An amplifier includes a load device, an operational amplifier, a current source, and a bipolar transistor. The operational amplifier has a first input terminal connected to a first input node that receives an input current, and a second input terminal connected to a second input node that receives a reference voltage. The current source is connected to an output of the operational amplifier. The operational amplifier, the current source, and the bipolar transistor form a feedback loop that generates and maintains a bias voltage on the first input node based on the reference voltage applied to the second input node. The bipolar transistor amplifies the input current received on the first input node, and generates an amplified input current. The load device converts the amplified input current to an output voltage, wherein the output voltage is used to sense the input current.

Abstract: In described embodiments, data streams with irregular patterns are processed by transformations defined by recursively changing processor state, or iteration level. The data transformations are applied to an arbitrary long portion of data, instead of small portions, that are defined directly by a current processor state. Embodiments combine small parts of, for example, puncturing/repetition patterns into a pattern of bigger parts and apply these patterns of bigger parts to relatively large portions of input data.

Abstract: A hard disk drive or other disk-based storage device comprises a storage disk, a read/write head configured to read data from and write data to the disk, and control circuitry coupled to or otherwise associated with the read/write head. The control circuitry comprises a write driver configured to generate a write signal for data to be written to the storage disk, and a multiple-slope transition controller associated with the write driver and configured to control a data transition in the write signal such that the data transition comprises at least two different segments each having a different slope, with the transition controller comprising separate slope control mechanisms for each of the segments. By way of example, the data transition may comprise a dual-slope transition having first and second segments arranged sequentially between a start point and an end point of the data transition.

Abstract: A digital-to-analog converter (DAC) has a pulse-width encoder that generates a charging pulse having a pulse width proportional to the DAC's digital input value. The charging pulse controls a charging switch that selectively connects a current source to a capacitor for the duration of the charging pulse. At the end of the charging pulse, a voltage corresponding to the charge stored in the capacitor forms the DAC's analog output signal. Such DACs can be configured (1) with negative-gain amplifiers across the capacitor to form a negative feedback loop, (2) with multiple parallel current sources, and/or (3) in differential architectures.

Abstract: Disclosed is an apparatus and method for estimating railway vehicle masses, the method comprising checking if a train has entered an initial acceleration section and a straight section, receiving a speed of the train, each acceleration of the plurality of railway vehicles and each traction of the plurality of railway vehicles, dynamically modeling the train, and estimating masses of the plurality of railway vehicles and rail gradient.

Abstract: Methods and apparatus for packing received Serial Attached SCSI (SAS) frames in buffers for transmission to a host system memory. SAS frames are received from another SAS device and stored in a frame buffer memory. User data in the received frames has appended SCSI Data Integrity Fields (DIF information) to enhance reliability. Features and aspects hereof use the DIF information to validate the user data and then strip the DIF information to densely pack the validated user data in a DMA staging buffer for transmission to a host's system buffer memory using DMA features of the SAS device. The DMA circuit is programmed and started when the staging buffer is filled to at least a threshold amount of data to thereby improve efficacy of the DMA transfer performance. Other criteria may also be employed to determine when to start the DMA circuit.

Abstract: Various embodiments of the present invention provide apparatuses and methods for processing data in a multi-path data processing circuit. For example, an apparatus is disclosed that includes a first filter operable to process a first digital data stream to yield a first filtered digital data stream, a second filter operable to process a second digital data stream to yield a second filtered digital data stream, wherein the first and second digital data stream are representative of a same data set and wherein the first and second digital data stream have a different phase, a combining circuit operable to combine the first filtered digital data stream and the second filtered digital data stream to yield a combined data stream, and a data detector operable to detect a data sequence in the combined data stream.

Abstract: A system and method for allocating transaction ID in a system with a plurality of processing modules is disclosed. In one embodiment, a method for assigning transaction ID to a processing module in a network on a chip system (NOCS) with a plurality of processing modules is disclosed. An address space is provided to each of the processing modules. A portion of the address space is selected. A subset of the selected portion of the address space for each of the processing module is selected as Valid Bits. The Valid Bits of the processing module is associated to a transaction ID.

Abstract: Described embodiments provide a wideband code division multiple access (W-CDMA) system, that employs an interleaving rule having a modified pruning algorithm. Interleaving, by pruning a sequence of bits in the W-CDMA system, includes determining a non-pruned interleaved vector having a length N. The determination of the non-pruned interleaved vector is based on a received length of an input vector from the sequence of bits. The input vector is padded. An interleaver generates a pre-pruned interleaved vector having a length equal to the length N, wherein the pre-pruned interleaved vector is a function of the padded input vector and the non-pruned interleaving vector. The interleaver prunes one or more elements from the pre-pruned interleaved vector based on a corresponding pruning indication in a pruning indication table, thereby providing a pruned interleaved vector as a portion of the interleaved sequence of bits.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a data decoder circuit. The data decoder circuit is operable to: apply a decoding algorithm to a decoder input on a first decoder iteration to yield a first decoder output; compress an output derived from the first decoder output to yield a compressed decoder output; de-compress the compressed decoder output to yield a second decoder output; and apply the decoding algorithm to the second decoder output to yield a third decoder output.

Abstract: In described embodiments, a transceiver includes an eye monitor, clock and data recovery, and adaptation modules. Data sampling clock phase and error clock phase determined from a data eye are decoupled in the transceiver during a sampling phase correction process. Decoupling these clock phases during the sampling phase correction process allows relative optimization of system equalization parameters without degradation of various adaptation algorithms. Such adaptation algorithms might be employed for received signal gain and equalization such as, for example, Decision Feedback Equalizer (DFE) adaptation. Deriving the data sampling clock and error clock phases from the same clock generation source and with independent clock control enables an iterative sampling phase correction process that allows for accelerated clock and data recovery (CDR) without disturbing the data eye shape.

Abstract: Methods and systems for device driver compilation dispensation of consumable compositions are provided. A method for compiling device drivers may include, but is not limited to: (a) installing a host OS on a compiler server; (b) installing a plurality of target OS on the compile server; (c) installing a dynamic kernel module support package (DKMS) on the compile server for at least one of the plurality of target OS; (d) compiling a driver module on the compile server for a first target OS of the plurality of target OS; and (e) compiling a driver module on the compile server for a second target OS of the plurality of OS.