Abstract: Techniques are described for increasing a lifetime of blocks of memory. In operation, respective life expectancy scores for each of the blocks are calculated based at least in part on a respective number of times each of the blocks is respectively erased, and further based at least in part on at least one other factor that affects the lifetime of the blocks. An order to write and recycle the blocks is determined, based at least in part on at least some of the respective lifetime expectancy scores. A total amount of the blocks that are erased and written is minimized while lifetime expectancy score variation between the blocks is equalized.

Abstract: Various embodiments of the present invention provide systems and methods for a data processing system with thermal control. For example, a data processing system with thermal control is disclosed that includes a number of data processors and a scheduler, which is operable to determine the power consumption of the data processors and to switch the data processing system from a first mode to a second mode and from the second mode to a third mode. The data processing system consumes less power in the third mode than in the first mode. The second mode prepares the data processing system to enter the third mode.

Abstract: A common actuator system of multi switches for a switchgear is capable of selectively opening or closing the plurality of switches using a single common actuator motor. The actuator system includes a single actuator motor providing a rotational force for commonly opening or closing the plurality of switches and having an output shaft, a plurality of link members provided to correspond to the plurality of switches, respectively, to transfer the rotational force of the actuator motor to the plurality of switches, a selective power transfer mechanism to selectively connect one of the plurality of link members to the actuator motor, and a rotational-linear force conversion mechanism to convert the rotational force of one of the plurality of link members into a linear force for opening or closing a corresponding switch and providing the linear force to the switch.

Abstract: Disclosed is a method for controlling an inverter, the method including, calculating the number of PWM pulses from a current frequency of the inverter, compensating the number of PWM pulses using a predetermined number of pulses when the number of PWM pulses is less than the predetermined number of pulses, and calculating a new frequency of the inverter using the compensated number of PWM pulses.

Abstract: A firmware updating method for a digital protective relay having a plurality of modules includes receiving firmware update related information from a master device, notifying necessity of firmware update to a target module having a firmware to be updated based on the firmware update related information, receiving a firmware update ready message from the target module, and downloading a firmware from the master device into the target module and installing the downloaded firmware. According to the method, without opening a distributing board or removing an enclosure of a digital protective relay for updating a firmware of the digital protective relay, reduction of time and costs for on-site engineering and maintenance can be expected.

Abstract: A SAS expander or initiator places PHYs in a wide port into a persistent reduced power state by signaling to the connected SAS device that the SAS expander or initiator intends to route data traffic through other PHYs in the wide port. The SAS expander or initiator and connected SAS device agree to disuse certain PHYs so that the PHYs enter a reduced power state according to SAS standards.

Abstract: The present invention is a configurable binary BCH encoder having a variable number of errors. The encoder may implement a universal multipole block which may be configured for receiving an error number input, which may include a maximum error number limit for the encoder, and for calculating a plurality of error coefficients based on the error number input. The encoder may be further configured for receiving a plurality of information bits of an information word. The encoder may be further configured for transmitting/outputting a first (ex.—unmodified) subset of the information bits as an encoder output. The encoder may be further configured for calculating a plurality of parity bits based on a second subset of the information bits and the error coefficients. The encoder may be further configured for transmitting/outputting the calculated parity bits as part of the encoder output.

Abstract: The present invention provides a method for digitally obtaining contours of fabricated polygons. A GDS polygon described in a Geographic Data System (GDS) file is provided. Based on the GDS polygon, a plurality of identical polygons is fabricated with the same fabrication process such that shapes of the plurality of identical polygons are altered by optical effects in the same or similar way. The plurality of identical polygons forms poly-silicon gates of a plurality of test transistors. The position of source and drain islands along a length of a poly-silicon gate for each of the plurality of test transistors is different. Using Automated Test Equipment (ATE), a digital test is performed on a circuit including the plurality of test transistors to obtain test responses, the test responses being raw digital data. The test responses may be displayed in a histogram reflecting a contour of the plurality of identical polygons or post-processed to reconstruct a contour of the plurality of identical polygons.

Abstract: Various embodiments of the present invention provide systems and methods for calculating and/or modifying fly height. For example, a circuit for calculating fly height is disclosed that includes: a first pattern detector circuit, a second pattern detector circuit, a first pattern fly height calculation circuit, a second pattern fly height calculation circuit, a first averaging circuit, a second averaging circuit, and a combining circuit.

Abstract: A method for detecting a failure in a serial topology. The method may comprise sending a predetermined pattern to a plurality of devices communicatively connected to an initiator in a serial topology; receiving a return result from each of the plurality of devices in response to the predetermined pattern; recognizing a problem associated with a particular device among the plurality of devices, the problem being recognized based on the return result from the particular device; sending a plurality of test patterns to the particular device; receiving a plurality of test results from the particular device in response to the plurality of test patterns; and determining a cause of the problem based on the plurality of test results, the cause of the problem being at least one of: a cable failure and a device failure.

Abstract: A closed loop dynamic interconnect bus allocation method and architecture for a multi layer SoC is disclosed. In one embodiment, a system on chip (SoC) includes multiple masters, multiple slaves, multiple buses, and an interconnect module coupled to multiple masters and multiple slaves via multiple buses. The interconnect module includes an arbiter. The SoC also includes an inner characteristic bus coupled to the plurality of masters, the plurality of slaves and the interconnect module. The interconnect module receives on-chip bus transactions substantially simultaneously from the multiple masters to be processed on one or more of the multiple slaves via the multiple buses. The interconnect module also receives inner characteristic information of the on-chip bus transactions via the inner characteristic bus.

Abstract: A RAID system is provided in which the RAID controller of the system causes a predetermined number, N, of IO commands to be queued in a memory element, where N is a positive integer. After the N IO commands have been queued, the RAID controller writes N locks associated with the N IO commands in parallel to a service memory device. The RAID controller then writes N stripes of data and parity bits associated with the N IO commands to the PDs of the system to perform striping and parity distribution. If a catastrophic event, such as a power failure, occurs, the RAID controller reads the locks from the service memory device and causes parity to be reconstructed for the stripes associated with the locks. These features improve write performance while preventing the occurrence of data corruption caused by write holes.

Abstract: The present invention is related to systems and methods for applying two or more data decode algorithms to a processing data set.

Abstract: Various embodiments of the present invention provide systems and methods for determining head polarity. As an example, a head polarity detection circuit includes: a first computation circuit, a second computation circuit, and an inversion determination circuit. The first computation circuit is operable to sum an absolute value of each sample of a first subset of a series of data samples corresponding to a first phase of an analog input to yield a first sum, and the second computation circuit is operable to sum an absolute value of each sample of a second subset of the series of data samples corresponding to a second phase of the analog input to yield a second sum. The first phase is more than ninety degrees offset from the second phase.

Abstract: Methods and apparatus are provided for write-side intercell interference mitigation in flash memories. A flash memory device is written by obtaining program data to be written to at least one target cell in the flash memory; obtaining one or more bits of program data for at least one aggressor cell to be programmed later than the target cell: and precompensating for intercell interference for the target cell by generating precompensated program values. The aggressor cells comprise one or more cells adjacent to the target cell, such as adjacent cells in a same wordline as the target cell and/or cells in an upper or lower adjacent wordline to the target cell. The precompensated program values for the target cell are optionally provided to the flash memory.

Abstract: The present invention is directed to a method for implementing firmware in an expander system in such a way that a single hardware component (ex.—a chip) of the expander system may be presented as multiple virtual expanders to both upstream connected devices (ex.—HBAs) as well as downstream connected devices (ex.—disk drives).

Abstract: An apparatus generally including an internal memory and a direct memory access controller is disclosed. The direct memory access controller may be configured to (i) read first information from an external memory across an external bus, (ii) generate second information by processing the first information, (iii) write the first information across an internal bus to a first location in the internal memory during a direct memory access transfer and (iv) write the second information across the internal bus to a second location in the internal memory during the direct memory access transfer. The second location may be different from the first location.

Abstract: A method for pre-staging data includes obtaining a DST configuration of a virtual volume at a first point in time. The method also includes creating a Point-in-Time copy (PiT) in a destination storage pool when the virtual volume includes at least one PiT, or reconfiguring at least one virtual volume segment to contain a hot-spot. The virtual volume may or may not have PiTs. The method further includes recording the DST configuration, specifying the DST configuration be applied to the storage array at a second point in time, and applying the DST configuration to the storage array at the second point in time.

Abstract: Various embodiments of the present invention provide systems and methods for decoding data. As an example, a data processing circuit is disclosed that includes a multi-tier decoding circuit having a first tier decoding circuit operable to decode portions of an encoded data set exhibiting low row weight, and a second tier decoding circuit operable to decode portions of an encoded data set exhibiting high row weight.

Abstract: A method for communication between an initiator system and a block storage cluster may include receiving a first command at a first storage system included in a plurality of storage systems of the block storage cluster. The method may also include transmitting a referral response from the first storage system to the initiator system when at least a portion of the data associated in the first command is stored by a second storage system. The method may further include obtaining a segment start value and a corresponding port identifier based on the referral response, and directing a second command to at least a second storage system included in the plurality of storage systems of the block cluster.