Abstract: A system for, and method of, performing static timing analysis. In one embodiment, the system includes: (1) a CVS tool configured to determine a cell-based voltage supply corresponding to each of a plurality of cells in an integrated circuit design and (2) an STA tool configured to derate the each of the cells based on the corresponding cell-based voltage supply.

Abstract: Methods and apparatus for improved building of a hot spare storage device in a RAID storage system while avoiding reading of stale data from a failed storage device. In the recovery mode of the failed device, all data is write protected on the failed device. A RAID storage controller may copy as much readable data as possible from the failed device to the hot spare storage device. Unreadable data may be rebuilt using redundant information of the logical volume. Write requests directed to the failed device cause the addressed logical block address (LBA) to be marked as storing stale data. When a read request is directed to such a marked LBA, the read request returns an error status from the failed device to indicate that the data is stale. The RAID controller then rebuilds the now stale data for that LBA from redundant information of the logical volume.

Abstract: Provided are a method for compensating instantaneous power failure in medium voltage inverter and a medium voltage inverter system by using the same, the method for compensating instantaneous power failure in medium voltage inverter including a plurality of power cells supplying a phase voltage to a motor by being connected to the motor in series, the method including decreasing an output frequency of the plurality of power cells by as much as a predetermined value at a relevant point where an input voltage of the plurality of power cells is less than a reference value, decreasing the output frequency at a predetermined deceleration gradient, and maintaining the output frequency during restoration of input voltage as long as a predetermined time, in a case the input voltage is restored.

Abstract: A multi-tiered system of data storage includes a plurality of data storage solutions. The data storage solutions are organized such that the each progressively faster, more expensive solution serves as a cache for the previous solution, and each solution includes a dedicated data block to store individual data sets, newly written in a plurality of write operations, for later migration to slower data storage solutions in a single write operation.

Abstract: A method of estimating a profit margin for an IC chip includes providing design, manufacturing and financial input data for the IC chip and determining a ratio of performing to manufactured IC chips using chip yields apart from timing. The method of estimating a profit margin also includes characterizing IC chip performance corresponding to clock timing and on-chip-variation (OCV) margins and calculating price and costs corresponding to design, manufacturing and testing of the IC chip. Additionally, the method of estimating a profit margin includes generating a profit margin based on the price and costs. A method of maximizing a profit margin for an IC chip is also included.

Abstract: A phase shift transformer in a multi-level medium voltage inverter is disclosed, wherein structure is modularized to provide layout freedom and to reduce volume and weight of an entire system, and a continuous operation of a motor is enabled, even if one module is faulted.

Abstract: The present invention is directed to a method for optimizing thermal management for a storage controller cache of a data storage system. The method allows for pending writes of a storage controller to be selectively provided to solid-state device (SSD) module(s) of the controller in a manner which allows operating temperatures of the SSD module(s) to be maintained within a thermal envelope.

Abstract: Described embodiments provide a method of assigning tasks to queues of a processing core. Tasks are assigned to a queue by sending, by a source processing core, a new task having a task identifier. A destination processing core receives the new task and determines whether another task having the same identifier exists in any of the queues corresponding to the destination processing core. If another task with the same identifier as the new task exists, the destination processing core assigns the new task to the queue containing a task with the same identifier as the new task. If no task with the same identifier as the new task exists in the queues, the destination processing core assigns the new task to the queue having the fewest tasks. The source processing core writes the new task to the assigned queue. The destination processing core executes the tasks in its queues.

Abstract: A device and method wherein a thermo electric generator device is disposed between stacks of a multiple level device, or is provided on or under a die of a package and is conductively connected to the package. The thermo electric generator device is configured to generate a voltage by converting heat into electric power. The voltage which is generated by the thermo electric generator can be recycled back into the die itself, or to a higher-level unit in the system, even to a cooling fan.

Abstract: In one embodiment, a reconfigurable adder has first and second five-bit non-reconfigurable adders and is selectively configurable to operate in a five-bit mode or a ten-bit mode. In five-bit mode, the first non-reconfigurable adder adds first and second messages to generate a first sum, and the second non-reconfigurable adder adds third and fourth messages to generate a second sum. In ten-bit mode, the first non-reconfigurable adder adds a first half of a first ten-bit message and a first half of a second ten-bit message to generate a first partial sum and a carry-over bit. The second non-reconfigurable adder adds a second half of the first ten-bit message, a second half of the second ten-bit message, and the carry-over bit to generate a second partial sum. A ten-bit sum is then generated by combining the first and second partial sums.

Abstract: Certain embodiments of the present invention are efficient run-time methods for creating and updating a RAM list of dominant trapping-set profiles for use in (LDPC) list decoding. A decoded correct codeword is compared to a near codeword to generate a new trapping-set profile, and the profile written to RAM. Record is kept of how many times RAM has been searched since a profile was last matched. Profiles that have not been matched within a specified number of searches are purge-eligible. Purge-eligible profiles are further ranked on other factors, e.g., number of times a profile has been matched since it was added, number of unsatisfied check nodes, number of erroneous bit nodes. If there is insufficient free space in RAM to store a newly-discovered profile, then purge-eligible profiles are deleted, beginning with the lowest-ranked profiles, until either (i) sufficient free space is created or (ii) there are no more purge-eligible profiles.

Abstract: A delay locked loop generates a voltage on a common node as a function of a phase difference between a reference input and a feedback input. A first voltage-controlled delay line coupled between the reference input and the feedback input and has a first delay, which is controlled by the voltage on the common node. A second voltage-controlled delay line is selectively coupled in series with the first delay line, between the reference input and the feedback input, as a function of a test control input. The second delay line has a second delay, which is controlled by the voltage on the common node.

Abstract: A bus arbitration system, a method of connecting a master device and a peripheral over a bus system of an IC and an IC is provided. In one embodiment, the bus arbitration system includes: (1) a bus system configured to couple master devices to peripherals, port arbiters coupled to the bus system, wherein each of the port arbiters uniquely corresponds to one of the peripherals and is configured to manage access to the uniquely corresponding peripheral and a request splitter configured to receive connection requests from the master devices for the peripherals and direct the connection requests to a specific one of the port arbiters according to a port identifier associated with each of the connection requests.

Abstract: An IC adapted for self-monitored burn-in includes a first memory and at least one BIST circuit coupled to the memory and operative to test the IC by executing a burn-in test and to generate test results indicative of at least one parameter of the burn-in test. The test results are at least temporarily stored in the first memory as a function of a first control signal.

Abstract: Several methods and a system to implement data compression inline with an eight byte data path are disclosed. In one embodiment, a method includes acquiring a data from a host. In addition, the method includes applying an eight byte data path to the data. The method also includes compressing the data inline. The method may further include writing the data in a memory through a memory controller using a RAID engine. The method may also include manipulating the data through the RAID engine. In addition, the method may include reading the data through a Serial Attached SCSI (SAS) core. The method may further include writing the data to a non-volatile storage. The method may include applying a compression technique based on a data history. The method may also include maintaining a consistent order of a sequence of the data during a data compression operation and a decompression operation.

Abstract: Provided is a network system and a method for determining a network path, the network system including a plurality of extension units, each containing dualized basic units and dualized extension Ethernet modules, a first ring network connected by a first basic unit and a plurality of first extension Ethernet modules, and a second ring network connected by a second basic unit and a plurality of second extension Ethernet modules, wherein the first extension Ethernet module or the second extension Ethernet module transmits or receives data along a network path determined by judging, by the first extension Ethernet module or the second extension Ethernet module, if the first ring network is connected to the second extension Ethernet module using an intrinsic number of each extension Ethernet module.

Abstract: An electronic device package 100 comprising a lead frame 105 having at least one lead 110 with a notch 205. The notch includes at least one reentrant angle 210 of greater than 180 degrees and the notch is located distal to a cut end 1010 of the lead.

Abstract: Systems and methods are hereby provided for enclosures having integrated handle features for storing one or more storage devices. The system includes a rigid frame and multiple bays. Each bay includes a body movably attached to the frame, wherein repositioning of the body with respect to the frame is restricted by at least one holding element of the frame to a limited range of motion. The body defines a receptacle for receiving and holding a storage device. Each bay also includes a lever arm rotatably attached to the frame, the lever arm comprising a cam surface to engage with the body and to move the body upon rotation of the lever arm. When the lever arm achieves a first position, the body engages the storage device with a communication channel, and when the lever arm achieves a second position, the body disengages the storage device from the communication channel.

Abstract: Higher-level redundancy information computation enables a Solid-State Disk (SSD) controller to provide higher-level redundancy capabilities to maintain reliable operation in a context of failures of non-volatile (e.g. flash) memory elements during operation of an SSD implemented in part by the controller. For example, a first computation is an XOR, and a second computation is a weighted-sum. Various amounts of storage are dedicated to storing the higher-level redundancy information, such as amounts equivalent to an integer multiple of flash die (e.g. one, two, or three entire flash die), and such as amounts equivalent to a fraction of a single flash die (e.g. one-half or one-fourth of a single flash die).

Abstract: In one embodiment, a communications system has a write path and a read path. In the write path, a local/global interleaver interleaves a user data stream, and an error-correction (EC) encoder encodes the user data stream to generate an EC codeword. A local/global de-interleaver de-interleaves the parity bits of the EC codeword, and both the original un-interleaved user data and the de-interleaved parity bits are transmitted via a noisy channel. In the read path, a channel detector recovers channel soft-output values corresponding to the codeword. A local/global interleaver interleaves the channel values, and an EC decoder decodes the interleaved values to recover the original codeword generated in the write path. A de-multiplexer de-multiplexes the user data from the parity bits. Then, a local/global de-interleaver de-interleaves the user data to obtain the original sequence of user data that was originally received at the write path.