Abstract: An apparatus comprising a write data buffer circuit, a memory, and a read data buffer circuit. The write data circuit may be configured to present data in a second format in response to data received in a first format. The memory may be configured to (i) receive the data in the second format and (ii) present the data in the second format. The read data buffer circuit may be configured to (i) receive data in the second format and (ii) present data in a third format. The memory may be configured to allow two reads or two writes during a single clock cycle of reference clock without encountering a data overflow condition.

Abstract: A method of designing an integrated circuit and a model of an integrated circuit block, an electronic design automation tool, an apparatus and a computer-readable medium are disclosed herein. In one embodiment, the method of designing an integrated circuit includes: (1) generating a timing budget for the integrated circuit employing designer input of the integrated circuit, (2) establishing design constraints for a block of the integrated circuit employing the timing budget, (3) creating an input and output timing budget for the block employing the design constraints, (4) combining implementation information for the integrated circuit based on designer knowledge with the input and output timing budget to generate an updated input and output timing budget and (5) generating a model of the block based on the updated input and output timing budget.

Abstract: Techniques are described for increasing a lifetime of blocks of memory. In operation, respective life expectancy scores for each of the blocks are calculated based at least in part on a respective number of times each of the blocks is respectively erased, and further based at least in part on at least one other factor that affects the lifetime of the blocks. An order to write and recycle the blocks is determined, based at least in part on at least some of the respective lifetime expectancy scores. A total amount of the blocks that are erased and written is minimized while lifetime expectancy score variation between the blocks is equalized.

Abstract: An apparatus comprising a plurality of buffers and a memory controller. The plurality of buffers may each be configured to generate an access request signal in response to a respective one of a plurality of channel requests received from a respective one of a plurality of clients. The memory controller circuit may be configured to generate a clock enable signal in response to the plurality of access request signals. The clock enable signal may be configured to initiate entering and exiting a power savings mode of a memory circuit.

Abstract: A method of generating a motion menu in a low memory environment. The method generally includes the steps of (A) generating a plurality of encoded streams in a buffer by encoding a fixed duration from each of a plurality of title streams received in a video program, (B) generating a plurality of thumbnails frames in the buffer by decoding each of the encoded streams and (C) generating the motion menu in the buffer by combining one of the thumbnail frames from each respective one of the encoded streams into a respective one of plurality of menu frames such that a sequential display the menu frames appears as a plurality of thumbnails having dynamic content in the motion menu.

Abstract: The present invention is a device for detecting short burst errors. The device includes a first signal input, wherein the first signal input is configured to receive a first signal. The device includes a second signal input, wherein the second signal input is configured to receive a second signal. The device includes a logic gate, wherein the logic gate is operable for receiving the first signal via the first signal input, receiving the second signal via the second signal input, and generating a logic output gate signal based on the received first signal and the second signal. Furthermore, the device includes a filter, wherein the filter is configured for receiving the logic output gate signal from the logic gate and generates a filter output signal based upon the received logic output gate signal, wherein the filter output signal is operable for flagging errors.

Abstract: A method and systems of adaptation of an active power supply set using an event trigger are disclosed. In an embodiment, a method includes providing power to a system load using an active power supply set. The active power supply set includes a power supply in an active mode. The method also includes detecting an event trigger. In addition, the method includes increasing a power mode of an additional power supply when the event trigger is detected. The method may include detecting an additional event trigger and decreasing the power mode of a unit of the active power supply set when the additional event trigger is detected.

Abstract: The present disclosure describes a system and method for allocating volume pieces across a redundant array of inexpensive discs (RAID). A method for allocating volume pieces across a redundant array of inexpensive discs (RAID) may comprise: (a) associating one or more volume pieces of a first logical volume with a first set of drives in a drive group; and (b) associating one or more volume pieces of a second logical volume with a second set of drives in the drive group, wherein the first set of drives in the drive group includes at least one drive which is not a member of the second set of drives in the drive group.

Abstract: The present disclosure is directed to a system and a method for optimizing redundancy restoration in distributed data layout environments. The system may include a plurality of storage devices configured for providing data storage. The system may include a prioritization module communicatively coupled to the plurality of storage devices. The prioritization module may be configured for determining a restoration order of at least a first data portion and a second data portion when a critical data failure occurs. The system may include a restoration module communicatively coupled to the plurality of storage devices and the prioritization module, the restoration module configured for restoring at least the first data portion and the second data portion based upon the restoration order.

Abstract: An iterative PCCC encoder includes a first delay line operative to receive at least one input data sample and to generate a plurality of delayed samples as a function of the input data sample. The encoder further includes a second delay line including a plurality of delay elements connected in a series configuration. An input of a first one of the delay elements is adapted to receive a sum of first and second signals, the first signal generated as a sum of the input data sample and at least one of the delayed samples, and the second signal generated as an output of a single one of the delay elements. A third delay line in the encoder is operative to generate an output data sample as a function of the sum of the first and second signals and a delayed version of the sum of the first and second signals.

Abstract: An apparatus for performing data caching comprises at least one cache memory including multiple cache lines arranged into multiple segments, each segment having a subset of the cache lines associated therewith. The apparatus further includes a first plurality of counters, each of the counters being operative to track a number of active cache lines associated with a corresponding one of the segments. At least one controller included in the apparatus is operative to receive information relating to the number of active cache lines associated with a corresponding segment from the first plurality of counters and to implement a cache segment replacement policy for determining which of the segments to replace as a function of at least the information relating to the number of active cache lines associated with a corresponding segment.

Abstract: An electronic device package 100 comprising a lead frame 150 having at least one lead 110 with a notch 205. The notch includes at least one reentrant angle 210 of greater than 180 degrees and the notch is located distal to a cut end 1010 of the lead.

Abstract: A method for reducing a timing violation in a negative slack path from an integrated circuit design, by identifying the negative slack path in the integrated circuit design with a processor, and then identifying positive slack paths by determining timing slack for the paths that are disposed before and after the negative slack path. A prediction is made as to whether margin can be obtained from the positive slack paths by performing additional timing optimization on the positive slack paths, and it is determined whether that margin is sufficient to reduce the timing violation to at least a desired level. If the margin is sufficient, then additional timing optimization is performed on the positive slack paths, and the margin is used to manipulate the clock skew and reduce the timing violation on the negative slack path.

Abstract: A global power distribution network in an integrated circuit comprising a first layer of conductive material and a second layer of conductive material. The first layer of conductive material may be (i) coupled to one or more power supplies and (ii) configured to form a plurality of first rails of a mesh. The first rails may (a) supply power to one or more components of a core logic of the integrated circuit, (b) be aligned with a first axis of the integrated circuit, and (c) have one or more parameters configured such that the mesh has a uniform voltage gradient from a perimeter of the integrated circuit to a center of the integrated circuit along the first axis. The second layer of conductive material may be (i) coupled to the one or more power supplies and (ii) configured to form a plurality of second rails of the mesh.

Abstract: Devices and systems for tool-less assembly of cable chains that are capable of being retractably stored. The device comprises a first contact element, a second contact element, and a lengthwise member. The first contact element is adapted for movable contact with a receiving member of a first cable chain segment. The second contact element is adapted for movable contact with a receiving member of a second cable chain segment. The lengthwise member is fixedly attached to the contact elements. When an angle between the first and the second cable chain segments is a first value, the lengthwise member experiences elastic deformation, generating a spring force at each contact element sufficient to pull the receiving member of the first cable chain segment rotatably towards the receiving member of the second cable chain segment, thereby reducing the angle between the first and the second cable chain segments to a second value.

Abstract: The present invention is directed to a method for implementing firmware in an expander system in such a way that a single hardware component (ex.—a chip) of the expander system may be presented as multiple virtual expanders to both upstream connected devices (ex.—HBAs) as well as downstream connected devices (ex.—disk drives).

Abstract: The present disclosure relates to an apparatus for fabricating an RFID label tag, the apparatus including an air assist pad adhering the RFID label to the label folding unit by discharging air of a predetermined pressure to an RFID label discharged from an RFID label printer, and a retrieving unit retrieving a defective RFID label by moving the defective RFID label to a position of the air assist pad, in a case an RFID label discharged from the RFID label printer is determined to be defective.

Abstract: Provided is a solar power conversion apparatus which includes at least one solar array receiving light and generating a DC power, a converter unit converting amplitude of the generated DC power, a multilevel inverter unit receiving the DC power from the converter unit to output AC power with multi levels and comprising a plurality of multilevel inverters, an AC filter insulating the inverter unit from a power grid, and a control unit applying a control signal to the converter unit and the multilevel inverter.

Abstract: An inverter communication system is provided. The system includes a plurality of inverters connected to each other through a communication line, and assigned with different original identifiers for mutual distinction, wherein each of the plurality of inverters: receives a data frame transmitted through a previous inverter; selectively transmits the received data frame to a subsequent inverter; generates a data frame to be transmitted when data to be transmitted to a specific inverter occur; and transmits the generated data frame to a subsequent inverter.

Abstract: Provided are a parallel communication device and a communication method thereof. The parallel communication device includes: a first receiving terminal receiving communication data transmitted through a master device; a first transmitting terminal transmitting the communication data received through the first receiving terminal to a slave device; a switch managing a communication line disposed between the first transmitting terminal and a plurality of slave devise; and a control unit confirming a first slave device to which the communication data are to be transmitted by using destination information in the communication data, and transmitting the received communication data to the confirmed first slave device.