Abstract: A method for computing and storing parity information in a RAID system includes dividing each segment in a stripe into a data block and a parity block, and storing in each parity block, parity information for a limited number of other data blocks in the stripe. A method for rebuilding data in a RAID system includes rebuilding the data from parity information and storing the rebuilt data on reserve portions of the remaining disks in the system.

Abstract: In one embodiment of a header-compression method, a timestamp value is divided by a stride value using a plurality of binary-shift operations corresponding to a Taylor expansion series of the reciprocal stride value in a base of ½. When the division-logic circuitry of an arithmetic logic unit in the corresponding communication device is not designed to handle operands that can accommodate the length of the timestamp and/or stride values, the header-compression method can advantageously be used to improve the speed and efficiency of timestamp compression in communication devices.

Abstract: A method of generating a model of a leadframe IC package, a leadframe modeler and an IC design system are disclosed. In one embodiment the method includes: (1) adding connectivity information to a geometric representation of a leadframe, wherein the connectivity information represents electrical connections between the IC die and leads of the leadframe and (2) formatting the leads to represent BGA point of contacts for the IC die.

Abstract: Disclosed are a power transmission device for a vacuum interrupter, and a vacuum breaker having the same. The device includes: a driving link coupled to an adjuster; a driven link coupled to a movable electrode of a vacuum interrupter; connection links configured to connect the driving link and the driven link with each other, and coupled to the driving link and the driven link such that an interval between the driving link and the driven link is varied; cams coupled to the connection links in a perpendicular direction; and cam guides having guide recesses for slidably coupling the cams, and configured to guide the interval between the driving link and the driven link to be changed.

Abstract: A search method for identifying an intra mode that can produce acceptable video-encoding quality for a pixel block while striking a proper balance between the quality and processor load. In a representative embodiment, the search method relies on a set of mode-selection rules for iteratively identifying candidate intra modes. Each identified candidate is evaluated based on a comparison of its sum of absolute differences (SAD) with the smallest SAD in the set of the previously identified candidates. The mode-selection rules use the comparison results as conditions that efficiently guide the search method toward an intra mode that is suitable for encoding the pixel block with acceptable video quality. On average, a representative embodiment of the search method disclosed herein is advantageously capable of finding a suitable intra mode in fewer iterations than a comparable prior-art search method.

Abstract: A gas insulated switchgear includes: an upper conductor; a lower conductor; a movable contact provided in the upper conductor; a fixed contact fixedly provided in the lower conductor; a moving side tulip contact provided in the movable contact; a moving side shield fixed to the upper conductor; a fixed side tulip contact provided in the fixed contact; a fixed side shield fixed to the lower conductor; and an insulating screen unit installed to selectively block the opening end of the moving side shield and covering an end of the movable contact when the movable contact is separated from the fixed contact.

Abstract: A lighted architectural mesh includes a plurality of interconnected wires forming a plurality of transverse openings. At least one light carrier is slidably received within at least one of said transverse openings. The at least one light carrier includes light nodes emitting light through the interstices on the front and/or rear side of the architectural mesh. The at least one light carrier further comprises a plurality of connecting elements, wherein the light emitter nodes of the at least one light element are releasably interconnected in series by the connecting elements.

Abstract: An apparatus having a first circuit and a second circuit is disclosed. The first circuit may (i) generate a decoded codeword by decoding a first codeword a plurality of times based on a respective plurality of erasure location vectors and (ii) assert a fail signal upon each failure of the decoding of the first codeword, the decoding comprising an error-and-erasure Reed-Solomon decoding. The second circuit may (i) generate a count of the assertions of the fail signal and (ii) generate the erasure location vectors based on (a) the count and (b) a plurality of reliability items corresponding to the first codeword.

Abstract: Disclosed is a switching gate driver of an IGBT device, including a resistor unit to control a gate current of the IGBT device; and a voltage reader that outputs a control signal to control a variable resistor unit of the resistor unit to the resistor unit, according to a collector-emitter voltage of the IGBT device.

Abstract: A voltage translator circuit includes an input stage adapted for receiving an input signal referenced to a first voltage supply, a first latch circuit adapted for connection with a second voltage supply and operative to at least temporarily store a logic state of the input signal, and a voltage clamp coupled between the input stage and the first latch circuit. The voltage clamp is operative to set a maximum voltage across the input stage to a prescribed level. The voltage translator circuit generates a first output signal at a first output formed at a junction between the first latch circuit and the voltage clamp. A second latch circuit is connected to the first output in a feedback configuration. The second latch circuit is operative to retain a logical state of the first output signal as a function of at least a first control signal supplied to the second latch circuit regardless of a state of the first voltage supply.

Abstract: A method for correcting at least one error in a data transmission over a packet-based communication network includes the steps of: generating a sequence of data packets for transmission over the packet-based communication network, the sequence of data packets being arranged into a plurality of packet frames, each of at least a subset of the packet frames including at least a primary data packet and a number of redundant data packets which is a function of a prescribed redundancy pattern, the subset of packet frames having a non-uniform distribution of redundant data packets therein; transmitting the sequence of data packets over the communication network; and recovering at least one missing data packet in the sequence of data packets using at least one corresponding redundant data packet in at least one subsequently received packet frame when the missing data packet is identified in a receiver of the sequence of data packets.

Abstract: In one embodiment, a circuit has multiple flip-flops with gated clock inputs controlled by an enable signal, where the clock signal is gated in order to reduce power consumption by the circuit. The circuit has an error detection and correction (EDC) module that is active when the enable signal is low in order to detect and correct soft errors of the flip-flops. The EDC module generates and stores an error-correction code based on the data outputs of the flip-flops. The EDC module then compares the stored error-correction code to a presently generated error-correction code, where if they are not identical, then the EDC (a) determines (i) that a soft error has occurred and (ii) which flip-flop suffered the soft error and (b) flips a corresponding error-correction signal to provide a correct corresponding output signal while the enable signal is low.

Abstract: Disclosed is an electronic magnetic contactor, the contactor including: an operation power supply unit inputting an operation power; an electronic switch driving unit receiving a power from the operation power supply unit to drive a power supply of a load; a switching unit switched by a pulse signal to drive the electronic switch driving unit; an operation state determination unit determining whether the electronic magnetic contactor is in an opened state or in a closed state; an input voltage sensing unit sensing an amplitude of an input voltage supplied from the operation power supply unit; and an input signal generation unit generating an input signal for determining whether the electronic magnetic contactor is inputted based on determined state by the operation state determination unit and the sensed amplitude by the input voltage sensing unit.

Abstract: Provided is an apparatus and method for controlling medium voltage inverter, whereby a frequency outputted by the medium voltage inverter is fixed, in a case an instantaneous power interrupt occurs while the medium voltage inverter drives a motor, and a voltage level of an AC power generated by the medium voltage inverter is reduced and outputted in response to a predetermined deceleration slope to control the medium voltage inverter.

Abstract: Provided is a gas circuit breaker. The gas circuit breaker includes a fixed part, a movable part, a piston, and a double compression mechanism. The fixed part includes a fixed arc contact and a first fixed contact maker. The movable part includes a movable arc contact selectively making contact with the fixed arc contact, a cylinder in which the movable arc contact is disposed, and a second fixed contact maker guiding a movement of the cylinder. The piston is disposed in the second fixed contact maker. The double compression mechanism is configured to move the piston in a direction opposite to a moving direction of the movable part when the movable part is moved to separate the fixed arc contact and the movable arc contact for interrupting a fault current.

Abstract: Provided is a fault current limiter, the limiter including a detector detecting an inflow of a fault current and transmitting a turn-on signal to a first switch and transmitting a turn-off signal to a power semiconductor element, the power semiconductor element changed to an OFF state by the turn-off signal, the first switch forming a current limiting circuit by being switched to an ON state by the turn-on signal, and a resistance element blocking the fault current, wherein the series connection between the resistance element and the first switch is connected in parallel to the power semiconductor element.

Abstract: Provided is a method for driving an IGBT, wherein a transient voltage applied across the IGBT is reduced by reducing a slope of a gate-emitter voltage of IGBT.

Abstract: Methods and circuits in an application circuit to compensate for skew in the transmission of serial data between field programmable gate arrays (FPGAs) in the application circuit. A clock signal source external to both FPGAs generates a clock signal applied to both FPGAs. A transmitting FPGA generates a serial data stream comprising the current values of a plurality of signals within the transmitting FPGA and transmits the serial data stream based on its clock signal. The receiving FPGA receives the serial data stream and applies a programmed delay to the received serial data stream to compensate for skew in received serial data stream relative to its clock signal. The programmed delay value may be determined at initialization (or reset) of the FPGAs by transmitting synchronization data from the first transmitting FPGA to the receiving FPGA. The receiving FPGA adjusts a programmable delay while receiving synchronization data until it sense bit and word alignment relative to its clock signal.

Abstract: Provided is a fault current limiter, the limiter including a detector detecting an inflow of a fault current and transmitting a turn-off signal to a power semiconductor element; the power semiconductor element changed to an OFF state by the turn-off signal; and a resistance element connected in parallel to the power semiconductor element to block the fault current.