Abstract: A method for dynamic storage tiering may include, but is not limited to: receiving an input/output (I/O) request from a host device; determining whether the I/O request results in a cache hit; and relocating data associated with the I/O request between a higher-performance storage device and lower-performance storage device according to the determination whether the data associated with the I/O request is stored in a cache.

Abstract: A circuit for use with a memory storage device including a magnetic storage medium and a write head operative to subject the magnetic storage medium to a magnetic field in response to an application of current to the write head, includes a write circuit operative to generate a write current supplied to the write head. The write current is characterized by a current waveform that reverses polarity in accordance with data to be stored on the magnetic medium. The circuit for use with the memory storage device further includes a degauss circuit operative to generate a degaussing current supplied to the write head. The degaussing current is characterized by a current waveform that oscillates between opposite polarities with an amplitude and a frequency that change over time.

Abstract: Provided is a protection coordination system, the system includes a current limiter arranged on a line between a first and a relays to limit a fault current generated to within a predetermined scope.

Abstract: A voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply includes an input stage for receiving the input signal, the input stage including at least first and second nodes, a voltage at the second node being a logical complement of a voltage at the first node. A load circuit is coupled with the input stage, the load circuit being operative to at least temporarily store a signal at the first and/or second nodes which is indicative of a logical state of the input signal. An output stage connected with the second node is operative to generate an output signal which is indicative of a logical state of the input signal. The voltage level translator circuit further includes a compensation circuit connected with the output stage and operative to balance pull-up and pull-down propagation delays in the voltage level translator circuit as a function of a voltage at the first node.

Abstract: An architecture includes a controller. The controller is configured to receive a microprogram. The microprogram is configured for performing at least one of hierarchical or a sequence of polynomial computations. The architecture also includes an arithmetic logic unit (ALU) communicably coupled to the controller. The ALU is controlled by the controller. Additionally, the microprogram is compiled prior to execution by the controller, the microprogram is compiled into a plurality of binary tables, and the microprogram is programmed in a command language in which each command includes a first portion for indicating at least one of a command or data transferred to the ALU, and a second portion for including a control command to the controller. The architecture and implementation of the programmable controller may be for cryptographic applications, including those related to public key cryptography.

Abstract: Described embodiments provide a network processor that includes a security protocol processor for staged security processing of a packet having a security association (SA). An SA request module computes an address for the SA. The SA is fetched to a local memory. An SA prefetch control word (SPCW) is read from the SA in the local memory. The SPCW identifies one or more regions of the SA and the associated stages for the one or more regions. An SPCW parser generates one or more stage SPCWs (SSPCWs) from the SPCW. Each of the SSPCWs is stored in a corresponding SSPCW register. A prefetch module services each SSPCW register in accordance with a predefined algorithm. The prefetch module fetches a requested SA region and provides the requested SA region to a corresponding stage for the staged security processing of an associated portion of the packet.

Abstract: The present invention is a cryptoengine configured for providing countermeasures against attacks, including: an input/output (I/O) control unit, a memory, a controller, and an Arithmetic Logic Unit (ALU). The memory is communicatively coupled with the I/O control unit, receives inputs from the I/O control unit, and provides outputs to the I/O control unit based upon the received inputs. The controller is communicatively coupled with the I/O control unit for transmitting and receiving control signals. The ALU includes a plurality of storage components and computational components. The ALU is communicatively coupled with the controller and receives commands from/transmits status bits and flags to the controller. The ALU is further communicatively coupled with the memory and is configured for providing output signals to/receiving input signals from the memory. Further, the cryptoengine is configured for being communicatively coupled with a host computing device.

Abstract: In one embodiment, a forward substitution component performs forward substitution based on a lower-triangular matrix and an input vector to generate an output vector. The forward substitution component has memory, a first permuter, an XOR gate array, and a second permuter. The memory stores output sub-vectors of the output vector. The first permuter permutates one or more previously generated output sub-vectors stored in the memory based on one or more permutation coefficients corresponding to a current block row of the lower-triangular matrix to generate one or more permuted sub-vectors. The XOR gate array performs exclusive disjunction on (i) the one or more permuted sub-vectors and (ii) a current input sub-vector of the input vector to generate an intermediate sub-vector. The second permuter permutates the intermediate sub-vector based on a permutation coefficient corresponding to another block in the current block row to generate a current output sub-vector of the output vector.

Abstract: An apparatus of modular trip mechanism and auxiliary mechanism for a circuit breaker comprises an auxiliary mechanism module including a first micro switch to output an electrical signal indicating an ON/OFF position of the circuit breaker, a first shaft contact lever mechanism to operate the first micro switch by contacting the switching shaft or receiving an artificial pressing force, a second micro switch to output an electrical signal indicating whether a trip operation of the circuit breaker has been performed, and a second lever to operate the second micro switch by contacting the switching shaft or receiving an artificial pressing force; and a trip mechanism module including an electromagnetic trip device to operate a trip bar to trigger the circuit breaker to a trip position in response to a trip control signal from an overcurrent relay or a test trip control signal from a test signal generating source.

Abstract: The present disclosure describes systems and methods for arbitrating between a plurality of devices competing for a system resource. Operations of the system and method may include, but are not limited to: initializing two or more previous grant request states; generating an access grant signal according to the two or more requests for access to the shared resource, two or more token states and the two or more previous grant request states; and generating an access grant signal according to the two or more requests for access to the shared resource, two or more token states and the two or more previous grant request states.

Abstract: A memory device includes at least one memory cell including a storage element electrically connected with a source potential line. A drive strength of the storage element is controlled as a function of a voltage level on the source potential line. The memory device further includes a clamp circuit electrically connected between the source potential line and a voltage source. The clamp circuit is operative to regulate the voltage level on the source potential line relative to the voltage source. A control circuit of the memory device is connected with the source potential line. The control circuit is operative to adjust the voltage level on the source potential line as a function of an operational mode of the memory device. A coarseness by which the voltage level on the source potential line is adjusted is selectively controlled as a function of at least a first control signal.

Abstract: A method for reducing noise in an output of a voltage regulator at frequencies above a closed loop bandwidth, by providing a noise injection path for injecting external noise into the voltage regulator, where the noise injection path becomes active at the frequencies above the closed loop bandwidth, where the noise injection path reduces the noise in the output of the voltage regulator.

Abstract: A clock-switching circuit having at least two inputs for receiving at least two different clock sources, an output for providing a selected one of the clock sources, and a switch for selecting the one of the inputs to provide on the output, the switch including elements that, prevent the providing of a truncated version of any of the clock sources on the output, always provide a clock signal on the output, and always maintain phase alignment and pulse ratio of the clock sources on the output.

Abstract: A method for correcting signals received on a channel. Signals are received along the channel and it is determined how many of the signals are outside a predetermined range relative to a plurality of predetermined constellation points (i.e., erasures). Then, the noise power is estimated the noise power based on the number erasures, and the noise power is used to correct the signals. Specifically, the estimated noise power can be used to correct the signals which have been determined to be outside the predetermined range and which have been determined to contain a large error component (i.e., based on distance from the closest constellation point). A look up table can be used to determine the correction to be applied, and a separate look up table can be used for each tone.

Abstract: A noise decreasing type electromagnetic switch includes a buffer disposed between an end of a stationary core and an end of a movable core facing the end of the stationary core so as to allow the movable core 150 to be elastically supported with respect to the stationary core. Accordingly, when the movable core contacts the stationary core, the buffer can be pressed and transformed to decrease impact and noise. Also, when the final operation is completed, the stationary core and the movable core are closely adhered, a performance of an actuator can be maintained.

Abstract: Methods and systems for improving performance in a storage system utilizing snapshots are disclosed by using metadata management of snapshot data. Specifically, various metadata structures associated with snapshots are utilized to reduce the number of IO operations required to locate data within any specific snapshot. The number of IO operations are reduced by allowing the various metadata structures associated with the temporally current snapshot to locate data directly within any temporally earlier snapshot or on the original root volume.

Abstract: Provided is an apparatus for controlling speed in induction motor in which tension command and friction loss compensation are used to calculate a torque limit relative to an output of a speed controller, which is then used to limit the speed of the induction motor, whereby a tension sensor and a position sensor are not used in the continuous processing line to improve performance of the vector control type induction motor.

Abstract: The present disclosure relates to an antenna system, and more particularly, to an RFID antenna system capable of improving a tag recognition rate of a shelf antenna system by generating energy of electromagnetic waves on a shelf, and a method for controlling the same. An antenna system according to an embodiment includes a first antenna configured to operate in response to a first control signal, a second antenna configured to operate in response to a second control signal and receive information from an RFID tag, and a reader unit configured to generate the first or second control signal and obtain the RFID tag information received through the second antenna.

Abstract: Provided is an apparatus for operating interior permanent magnet synchronous motor by receiving a first current command of a flux weakening control region I in a system including a detector measuring a position and a speed of a rotor of an IPMSM, the apparatus including a feedback unit transmitting over-modulated voltage information to a correction unit, the correction unit using the rotor speed and the over-modulated voltage information to correct the first current command to a second current command of a flux weakening control region II, a control unit controlling the second current command to output a voltage, a first limit unit limiting an output of the control unit to a maximum voltage synthesizable by an inverter unit, and the inverter unit applying a 3-phase voltage command for following a command torque to the IPMSM using an output of a voltage limit unit.

Abstract: Provided is an apparatus for operating interior permanent magnet synchronous motor in a system including a detector measuring a position and a speed of a rotor of an IPMSM, the apparatus including an output unit generating and outputting a current command driving a MTPA (Maximum Torque Per Ampere) based on the command torque, a correction unit correcting the current command outputted by the output unit, a feedback unit transmitting over-modulated voltage information to the correction unit, a control unit controlling the current command to output a voltage, a first limit unit limiting an output of the control unit using a maximum voltage synthesizable by an inverter unit, and the inverter unit applying a 3-phase voltage command for tracking a command torque to the IPMSM using an output of the first limit unit.