Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide data processing circuits that include a variable gain amplifier circuit, an analog to digital conversion circuit, a cosine component calculation circuit, a sine calculation circuit, and a zero gain start calculation circuit. The variable gain amplifier circuit is operable to apply a gain to a data input corresponding to a gain feedback value and providing an amplified output. The analog to digital conversion circuit is operable to convert the amplified output to a corresponding series of digital samples. The cosine component calculation circuit is operable to calculate a cosine component from the series of digital samples, and the sine component calculation circuit operable to calculate a sine component from the series of digital samples.

Abstract: An apparatus including a first circuit and a second circuit. The first circuit may be configured to generate an equalized signal in response to an input signal and an equalizer parameter signal. The equalizer parameter signal generally causes a cancellation of pre-cursor inter-symbol interference from a plurality of symbols in the input signal. The second circuit may be configured to generate (i) the equalizer parameter signal, (ii) a control signal and (iii) a data output signal in response to the equalized signal. The control signal generally causes an adjustment of the equalizer parameter signal. The adjustment of the equalizer parameter signal generally causes a decrease in the pre-cursor inter-symbol interference from the symbols.

Abstract: Methods and systems for advanced interrupt processing and scheduling are provided. The system comprises a memory operable to store interrupt priorities, an interface, and a processor operable to acquire incoming interrupts and to handle the incoming interrupts according to the interrupt priorities. The processor is also operable to receive interrupt processing criteria from the interface (sent, for example, from a device not directly coupled with the system), and to modify the interrupt priorities of the memory based upon the interrupt processing criteria without losing incoming processing requests for the system. Additionally, the processor is operable to process the incoming interrupts according to the modified interrupt priorities responsive to modifying the interrupt priorities.

Abstract: A semiconductor platform for implementing multiple-frequency operations includes multiple physical resources comprising embedded functions and a configurable transistor fabric. The transistor fabric includes at least first and second portions, the first portion being programmable to instantiate a first function having higher frequency operations than the second portion. The platform further includes multiple logical resources corresponding to the physical resources of the semiconductor platform and a configurable power mesh to support multiple frequency operations configurable from the transistor fabric. The power mesh includes at least first and second configurable grids. The first configurable grid is operable at a different frequency than the second configurable grid. The power mesh is modifiable, as a function of a desired performance of a customer's requirements, in a vicinity of the first portion of the configurable transistor fabric to support the first function having higher frequency operations.

Abstract: The present invention is a method for providing multi-pathing via Small Computer System Interface Input/Output (SCSI I/O) referral between an initiator and a storage cluster which are communicatively coupled via a network. The method includes receiving an input/output (I/O) at a first target device from the initiator via the network. The I/O includes a data request. The method further includes transmitting a SCSI I/O referral list to the initiator when data included in the data request is not stored on the first target device, but is stored on a second target device. The referral list includes first and second port identifiers for identifying first and second ports of the second target device respectively. The first and second ports of the target device are identified as access ports for accessing the data requested in the data request.

Abstract: A system may include information handling system devices connected together to form a computing cluster utilizing a SCSI interface. Each one of the information handling system devices may include an operating system kernel having a SCSI networking module for encapsulating Internet Protocol (IP) packets for transmitting between the information handling system devices. The system may also include SCSI hardware for connecting the information handling system devices together. The SCSI hardware may be configured to transmit the encapsulated IP packets between the information handling system devices.

Abstract: Disclosed herein is an electro-magnetic contactor and an electro-magnetic contactor monitoring system. The present disclosure may sense and display the status of input power that supplies electric energy to a power input end of the electro-magnetic contactor in real time, and when a failure occurs to generate a low voltage or over voltage, it may be sensed in real time to notify it to a user or the like, thereby allowing the user to monitor the status from a remote location. According to the present disclosure, it may be possible to prevent a load from being damaged by a fire due to a phenomenon of chattering in the electro-magnetic contactor, and eradicating a phenomenon that a coil of the contactor is damaged by a fire due to the over voltage, and minimizing losses that can be caused in a factory management system.

Abstract: Apparatus and devices for carrying a storage device and adapting it to a slot for a storage device having a different form factor. The system comprises an opening means for elastically deforming a shape of the system from an original shape so that the carrier may receive the storage device. The system also comprises restraining means for constraining the motion of the storage device within the system when the system returns to the original shape. Furthermore, the system comprises a spacing means for aligning the storage device with the slot while the storage device is restrained within the system.

Abstract: A method and/or an apparatus of core timing prediction is disclosed. In one embodiment, a method may include generating a core timing model of a core logic that is accurately transferable to any chip-level integration process. The method may reduce performance degradation and/or performance variation of the core logic caused by a number of interactions between core logic components and chip-level components in the chip-level integration process. In addition, the core timing model of the core logic may be generated by filling un-wired tracks with metal in any of an outermost layer of the core logic after a core logic routing and constructing a layer at least an area of and adjacent to any of the outermost layer of the core logic with grounded metal that is orthogonal to those of the metal used in the outermost layer of the core logic.

Abstract: Various embodiments of the present invention provide systems and methods for preparing and accessing super sector data sets. As an example, a data storage system including a storage medium is disclosed. The storage medium includes a first servo data region and a second servo data region separated by a user data region. The user data region includes at least a portion of a first codeword and a portion of a second codeword that are together associated with a common header data.

Abstract: An etchant for dielectrics, such as silicon dioxide, that leaves monocrystalline silicon surface exposed by the etchant free of etch damage, such as etch pits, when the etch is done in the presence of transition metals, such as copper, tungsten, titanium, gold, etc. The etchant comprises hydrofluoric acid and a source of halide anion, such as hydrochloric acid or a metal-halide. The etchant is useful in microelectromechanical system device fabrication and in deprocessing integrated circuits or the like.

Abstract: Described embodiments provide tracking and processing of commands received by a storage device. For each received command, the storage device determines one or more requested logical block addresses (LBAs), including a starting LBA and a length of one or more LBAs of the received command. The storage device determines whether command reordering is restricted. If command reordering is not restricted, the storage device processes the received commands. Otherwise, if command reordering is restricted, the storage device conflict checks each received command. If no conflict is detected, the storage device tracks and processes the received command. Otherwise, if a conflict is detected, the storage device queues the received command.

Abstract: A method and apparatus for synchronizing input/output commands is provided. An incoming command mask representing an incoming input/output command associated with a memory region is created. In response to a determination that a pending input/output command associated with the memory region is pending, a bitwise inversion operation is performed on the incoming command mask to form a modified incoming command mask. A bitwise AND operation is performed on the modified incoming command mask and the pending command mask to form a pending command locking mask associated with the pending input/output command. A bitwise OR operation is performed between an existing memory lock for a same type of commands and incoming command bit mask to form a new memory region lock.

Abstract: Described embodiments provide coherent processing of hash operations of a network processor having a plurality of processing modules. A hash processor of the network processor receives hash operation requests from the plurality of processing modules. A hash table identifier and bucket index corresponding to the received hash operation request are determined. An active index list is maintained for active hash operations for each hash table identifier and bucket index. If the hash table identifier and bucket index of the received hash operation request are in the active index list, the received hash operation request is deferred until the hash table identifier and bucket index corresponding to the received hash operation request clear from the active index list. Otherwise, the active index list is updated with the hash table identifier and bucket index of the received hash operation request and the received hash operation request is processed.

Abstract: Various approaches related to systems and methods for LDPC based data processing.

Abstract: An input port is assigned to a SAS expander device. An output port is assigned to the SAS expander device. The output port and the input port are defined to be paired with each other as a primary subtractive port. Only a SAS initiator address is programmed in the route table of the SAS expander. An OPEN command is sent out the output port upon receiving the OPEN command into the input port if the DEST of the OPEN command is not a direct attached device of the SAS expander device and the DEST is not in the route table of the SAS expander device. An OPEN command is sent out the input port upon receiving the OPEN command into the output port if the DEST of the OPEN command is not a direct attached device of the SAS expander device and the DEST is not in the route table of the SAS expander device.

Abstract: A system for managing a storage array having a set of storage components comprises a storage array controller, the storage array controller including: a first instance of a controller firmware on a virtual machine in a privileged domain, the privileged domain having access to hardware of the storage array; and a second instance of the controller firmware on a separate virtual machine in a first non-privileged array domain. The privileged domain is configured to inspect an I/O request and determine whether a target of the I/O request is an existing non-privileged array domain, to initiate launch of the first non-privileged array domain array when the I/O request does not relate to an existing non-privileged array domain, and to present available storage components to the first non-privileged array domain when the I/O request relates to the first non-privileged array domain.

Abstract: A method for compensating for jitter during DDR3 delay line training may include using a computer or processor to perform the steps of executing a plurality of tests for each one of a plurality of delay values for an interconnect delay between a Double-Data-Rate Three (DDR3) memory controller and a DDR3 Synchronous Dynamic Random Access Memory (SDRAM); accumulating a plurality of test results for each plurality of tests for each one of the plurality of delay values; determining a plurality of final test results, where each final test result is associated with an accumulated plurality of test results; and determining a working window edge for the interconnect delay between the DDR3 memory controller and the DDR3 SDRAM utilizing the plurality of final test results.

Abstract: Provided is an RTLS system using TDOA, the RTLS system tracking, by a positioning unit, a position of a transmitter based on a position signal transmitted by the transmitter, the system comprising a plurality of receivers receiving the position signal from the transmitter, and a gateway calculating a time difference of position signal arriving at the plurality of receivers from the transmitter and providing the time difference to the positioning unit.

Abstract: A method for distributing IO load in a RAID storage system is disclosed. The RAID storage system may include a plurality of RAID volumes and a plurality of processors. The IO load distribution method may include determining whether the RAID storage system is operating in a write-through mode or a write-back mode; distributing the IO load to a particular processor selected among the plurality of processors when the RAID storage system is operating in the write-through mode, the particular processor being selected based on a number of available resources associated with the particular processor; and distributing the IO load among the plurality of processors when the RAID storage system is operating in the write-back mode, the distribution being determined based on: an index of a data stripe, and a number of processors in the plurality of processors.