Abstract: Methods and structure for diagnosing errors in the initialization of DDR memory “on board” a storage controller or a storage expander are presented herein. The features and aspects discussed herein allow for the debugging of the DDR memory initialization. A memory diagnostic system is operable on a storage controller and includes an initialization module in communication with a firmware module of the storage controller. The memory diagnostic system is adapted to initialize a Double Date Rate (DDR) memory of the storage controller. The memory diagnostic system also includes an application programming interface adapted to retrieve initialization information from the initialization module and transfer the initialization information to a debug system via a direct communication link between the application programming interface and the debug system to diagnose the initialization of the DDR memory and to debug the initialization module based on the initialization information.

Abstract: A SAS expander for use in a SAS topology includes a receiving portion and a controller. The receiving portion is configured to receive a remote RAID instruction from a root host bus adapter. The controller is configured to execute the instruction to manage a RAID volume in accordance with a RAID management task specified by the instruction.

Abstract: A switching mechanism for a gas insulated switchgear includes: a stationary contactor having a stationary arc contactor portion and a stationary main contactor portion; a movable arc contactor which is linearly movable; a movable main contactor which is linearly movable; a cylinder rod which provides driving power for linear motion to the movable main contactor and the movable arc contactor; a connecting rod which is connected to the cylinder rod; a stationary cylinder having a hollow guide tube portion for guiding the linear motion of the cylinder rod and the connecting rod; and a spring which charges elastic energy when the movable main contactor and the movable arc contactor move to the contacting position and discharge the elastic energy when the movable main contactor and the movable arc contactor move to the separating position.

Abstract: Provided is a PLC simulator including a component configuration unit receiving a command from a user to controllably perform a simulation, and a simulation unit receiving a command from the component configuration unit to perform a simulation of a connected external PLC, whereby a user is provided with a convenient environment capable of simulating a variety of systems through reconfigurable component, and a user is capable of reducing a TCO (Total Cost of Ownership) by being provided with a testing environment maximally similar to that of an actual apparatus through application of external input conditions.

Abstract: A method of controlling spinning of data disk drives, a data storage system including multiple data disk drives and a power zone aware device are disclosed herein. In one embodiment, the power zone aware device includes: (1) a policy module configured to define at least one power zone in the data storage system and assign a power zone policy thereto and (2) a management module coupled configured to direct operation of data disk drives in the power zone based on the power zone policy.

Abstract: In described embodiments, filter parameters for a filter applied to a signal in, for example, a Serializer/De-serializer (SerDes) receiver and/or transmitter are generated based on real-time monitoring of a data eye. The real-time eye monitor monitors data eye characteristics of the signal present in a data path, the data path applying the filter to the signal. The eye monitor generates eye statistics from the monitored data eye characteristics and an adaptive controller generates a set of parameters for the filter of the data path for statistical calibration of the data eye, wherein the eye monitor continuously monitors the data eye and the adaptive controller continuously generates the set of parameters based on the eye statistics.

Abstract: Described embodiments provide reconstruction of logical-to-physical address mapping data for one or more sectors of a storage device at startup of a media controller. The sectors of the storage device are organized into blocks and superblocks and the address mapping data is stored in a volatile memory. At a startup condition of the media controller, a buffer layer module of the media controller allocates space in the volatile memory for one or more logical-to-physical address mapping data structures. A media layer module of the media controller determines a block type of each block of the storage device and places each block of the storage device into corresponding groups based on the determined block type of each block. The one or more blocks of each group are processed, and one or more address mapping data structures for the storage device are constructed in the allocated space in the volatile memory.

Abstract: An architecture includes a controller. The controller is configured to receive a microprogram. The microprogram is configured for performing at least one of hierarchical or a sequence of polynomial computations. The architecture also includes an arithmetic logic unit (ALU) communicably coupled to the controller. The ALU is controlled by the controller. Additionally, the microprogram is compiled prior to execution by the controller, the microprogram is compiled into a plurality of binary tables, and the microprogram is programmed in a command language in which each command includes a first portion for indicating at least one of a command or data transferred to the ALU, and a second portion for including a control command to the controller. The architecture and implementation of the programmable controller may be for cryptographic applications, including those related to public key cryptography.

Abstract: Various embodiments of the present invention provide systems and methods for servo data based harmonics calculation. For example, a method for calculating harmonics is disclosed that includes: providing a data processing circuit; receiving a first data set derived from a data source during a servo data processing period; performing a first harmonics calculation using the first data set to yield a first harmonics ratio; receiving a second data set derived from a source other than the previously mentioned data source during a user data processing period; performing a second harmonics calculation using the second data set to yield a second harmonics ratio; and calculating a ratio of the first harmonics ratio to the second harmonics ratio.

Abstract: A method of determining signal routing in an integrated circuit includes providing first coordinates of an input/output cell and second coordinates of an input/output pad to a parametric routing module. The parametric routing module receives at least one wire path parameter. The parametric routing module uses the at least one connection path parameter to determine a physical dimension of a wire path between the first coordinates and the second coordinates.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is discussed that includes a data detector circuit, a detector mimicking circuit, and an error calculation circuit. The data detector circuit is operable to perform a data detection process on a first signal derived from a data input to yield a detected output. The data mimicking circuit is operable to process a second signal derived from the data input to yield a mimicked output. The error calculation circuit is operable to calculate a difference between the second signal and a third signal derived from the mimicked output to yield a feedback signal. The feedback signal is operable to modify the data input during a subsequent period.

Abstract: Described embodiments provide a media controller for processing one or more data transfer requests received from at least one host device. The media controller includes a buffer to receive data of a data transfer request from a communication link and a command parser to generate one or more contexts corresponding to the data transfer request. The one or more contexts are stored in the buffer. At least one queue of the media controller includes a regular context queue for queuing regular-priority contexts, and a high-priority context queue for queuing high-priority contexts. A context manager coordinates processing of regular-priority contexts and high-priority contexts of the at least one queue based on context boundaries, wherein, when a context is processed at a context boundary, data corresponding to the processed context is data is transferred between the communication link and at least one of the buffer and the at least one storage media.

Abstract: A method for capturing data comprising the steps of (A) handling a call for a first operating system at a storage library, (B) routing the call from the storage library to a controller firmware, (C) sending a response to the call from the controller firmware to the storage library, and (D) storing the response in a data store box for later use by the storage library.

Abstract: A double-step CORDIC algorithm is implemented for conventional signed arithmetic using multiple iteration stages in which at least one stage implements decision postponing, in which the decision for each stage is delayed until the next stage. In one implementation, the decision for the previous stage is implemented in parallel with the execution of CORDIC equation functions for the current stage. Implementing the double-step CORDIC with decision postponing algorithm can increase the speed of the CORDIC function compared to prior-art CORDIC implementations.

Abstract: A method and system for tracking a sequence of bad blocks in a RAID system by storing the logical block address of the first bad block and the number of bad blocks in the sequence is disclosed. The method and system may also track multiple sequences of bad blocks by storing a memory pointer to the next sequence in each previous sequence in an expandable linked list configuration.

Abstract: A circuit breaker having a cradle, the circuit breaker comprises: an upper shutter and a lower shutter configured to open and close terminals of the cradle; an upper shutter operation link having one end connected to the upper shutter and another end rotatably coupled to a pivot; a lower shutter operation link having one end connected to the lower shutter and another end rotatably coupled to the pivot; and a shutter safety device comprising a coupling unit fixedly-coupled to the pivot, a rotation unit rotatably coupled to the coupling unit, and a link fixing unit provided at one end of the rotation unit, wherein the link fixing unit is to restrict rotation of the upper shutter operation link and the lower shutter operation link in a contacting manner.

Abstract: Provided is a system employed for authentication of a mobile terminal and a method using the same, wherein the method is such that an authentication code is received from a tag using a first communication type through a second communication type using a substantially same frequency band as that of the first communication type, and the authentication code is transmitted to a server of a mobile service provider to perform the authentication.

Abstract: Skip based control logic for first in first out buffer is disclosed. In one embodiment, a host controller interface (HCI) device includes an isochronous receive first in first out (IRFIFO) buffer. The IRFIFO buffer includes a storage for storing an isochronous data packet received from a guest device. Further, the IRFIFO buffer includes a write pointer for pointing to a write address of the storage for a write operation. Furthermore, the IRFIFO buffer includes a read pointer for pointing to a read address of the storage for a read operation. In addition, the IRFIFO includes a control logic for incrementing the read pointer by a value of a skip parameter of a skip register if the isochronous data packet is not valid for the read operation.

Abstract: Various embodiments of the present invention provide for extended life operation of multi-bit memory cells. As an example, some embodiments of the present invention provide electronic systems that include a plurality of multi-bit memory cells, an encoding circuit and a decoding circuit. Each of the plurality of multi-bit memory cells is operable to hold at least two bits. The encoding circuit is operable to receive a data input including at least two data bits, and to encode the two data bits as an encoded output to the plurality of multi-bit memory cells. The encoded output may be selected to be either a single two bit output representing the two bits, or a series of two two bit outputs representing the two bits. The decoding circuit is operable to reverse the encoding applied by the encoding circuit.

Abstract: An integrated circuit package substrate includes a first and an additional electrically conductive layer separated from each other by an electrically insulating layer, a contact pad formed in the first electrically conductive layer for making a direct connection between the integrated circuit package substrate and a printed circuit board, and a cutout formed in the additional electrically conductive layer wherein the cutout encloses an area that completely surrounds the contact pad for avoiding parasitic capacitance between the additional electrically conductive layer and the printed circuit board.