Abstract: Certain embodiments of the present invention are improved turbo-equalization methods for decoding encoded codewords. In one embodiment, in global decoding iteration i, the magnitude values of all decoder-input LLR values (Lch) are adjusted based on the number b of unsatisfied check nodes in the decoded codeword produced by global iteration i?1. The improved turbo-equalization methods can be used as the sole turbo-equalization method for a given global decoding session, or interleaved with other turbo-equalization methods.

Abstract: A method and disk drive for calibrating a phase of a clock in the disk drive. The phase of the clock in the disk drive is changed such that a rate of change for the phase is substantially constant. A pattern of data is written to a magnetic material in the disk drive after the rate of change for the phase becomes substantially constant and while changing the phase of the clock. A selected phase of the clock at which the pattern of data that is written on the magnetic material has a desired quality is identified using the rate of change for the phase, a first point in time at which a timing mark on the magnetic material is read, a second point in time at which the timing mark is read, and a third point in time at which the pattern of data has the desired quality.

Abstract: Skip based control logic for first in first out buffer is disclosed. In one embodiment, an isochronous data packet placed in an isochronous receive first in first out (IRFIFO) buffer coupled to an isochronous receive direct memory access (IRDMA) is detected. Further, a header of the isochronous data packet is read. Furthermore, a validity of the isochronous data packet is determined. Also, a read operation of remaining data of the isochronous data packet is skipped if the isochronous data packet is determined as invalid.

Abstract: One aspect provides an input/output cell. The input/output cell, in one example, includes an input/output layout boundary delineated on a substrate, wherein the input/output layout boundary defines a first side parallel and opposing a second side, a third side parallel and opposing a fourth side, wherein the first and second sides are substantially perpendicular the third and fourth sides. The input/output cell, in this example, further includes input/output transistors positioned within the input/output layout boundary over the substrate. The input/output cell, in this example, further includes first and second power conductors and first and second ground conductors located over the substrate, the first power conductor and first ground conductor extending entirely between the first and second sides and the second power conductor and second ground conductor extending entirely between the third and fourth sides.

Abstract: A memory device comprises a memory array and a phase distribution circuit coupled to the memory array. In one aspect, the phase distribution circuit is operative to control respective durations of a precharge phase and an active phase of a memory cycle of the memory array based on relative transistor characteristics of a tracked precharge transistor of a first conductivity type and a tracked memory cell transistor of a second conductivity type different than the first conductivity type. For example, the phase distribution circuit may comprise a first tracking transistor of the first conductivity type for tracking the precharge transistor of the first conductivity type and a second tracking transistor of the second conductivity type for tracking the memory cell transistor of the second conductivity type. The relative transistor characteristics may comprise relative strengths of the tracked precharge and memory cell transistors.

Abstract: A method of configuring a storage device is disclosed. The method generally includes the steps of (A) receiving a single data unit over a communication network, the data unit (i) being transferred via the communication network using a standard communication protocol, (ii) defining both (a) a plurality of new configuration items that define a new configuration of the storage device and (b) a command to be performed by the storage device and (iii) having a standard markup language format, (B) calculating at least one configuration change from a plurality of current configuration items to the new configuration items, the current configuration items defining a current configuration of the storage device, (C) adjusting the storage device into the new configuration based on the at least one configuration change and (D) performing a requested operation with the storage device in the new configuration in response to the command.

Abstract: Described embodiments provide encryption/decryption of data transferred between a media controller and a storage device. The media controller provides encryption/decryption based on a root key (RK). Storage in a one-time programmable (OTP) memory is provided as a plurality of un-burned slots. The OTP memory is initially provided without the RK, which is generated with a random number generator. A control module performs the steps of i) burning the RK to an initial slot of the OTP memory, and ii) validating the burned RK (bRK) stored at the initial slot based on a comparison of the RK and the burned RK. If the control module validates the burned RK, the burned RK is employed by the media controller. Otherwise, one or more subsequent slots of the OTP memory are burned with the RK until the control module validates the corresponding burned RK.

Abstract: A method to generate an erasure locator polynomial in an error-and-erasure decode. The method generally includes the steps of (A) storing current values in multiple registers at a current moment, (B) generating first values by multiplying each current value by a respective one of multiple constants, (C) generating second values by gating at least all but one of the first values with a current one of multiple erasure values of an erasure position vector, (D) generating next values by combining each one of the second values with a corresponding one of the first values, (E) loading the next values into the registers in place of the current values at a next moment and (F) generating an output signal carrying the current values at a last moment such that the current values form the coefficients of the erasure locator polynomial.

Abstract: Methods and apparatus are provided for CDR and equalization update qualification. A block of received data comprising a plurality of multiple tone patterns is processed. Equalization adaptation and/or updates to a timing recovery process can be selectively disabled if one or more of the multiple tone patterns exceed a corresponding predefined threshold.

Abstract: An electronic device includes an active layer located over a substrate with the active layer having a logic circuit and an eDRAM cell. The electronic device also includes a first metallization level located over the active layer that provides logic interconnects and metal capacitor plates. The logic interconnects are connected to the logic circuit and the metal capacitor plates are connected to the eDRAM cell. The electronic device additionally includes a second metallization level located over the first metallization level that provides an interconnect connected to at least one of the logic interconnects, and a bit line that is connected to the eDRAM cell. A method of manufacturing an electronic device is also included.

Abstract: An apparatus comprising an arbiter circuit, a protocol engine circuit and a channel router circuit. The arbiter circuit may be configured to determine a winning channel from a plurality of channel requests based on a first criteria. Each of the plurality of channel requests may represent a burst of data having a fixed length aligned to an address boundary of a memory. The protocol engine circuit may be configured to receive a signal from the arbiter circuit indicating the winning channel. The protocol engine circuit may also be configured to perform a memory protocol at a granularity equal to the burst of data. The channel router circuit may be configured to present the plurality of channel requests to the arbiter circuit and the protocol engine circuit.

Abstract: Provided is a PLC data log module and method for storing data in the same, wherein, in a case one or more storages among a plurality of outside storages is attached, a log data is stored in the attached outside storage, the log data is stored in the storage and check is made as to whether the log data is normally stored in the attached outside storage.

Abstract: A medium voltage inverter system is disclosed, the system including a coupled reactor magnetically connecting first and second reactors each connected to an output of first and second medium voltage inverters for driving a motor.

Abstract: Provided, according to the present invention, is an RTLS tag device generating a power through a shock applied to a piezoelectric element and transmitting tag information or an emergency signal to the wireless LAN APs, and a real time location system including an integrated management server receiving the tag information through the wireless LAN APs to extract location information of the RTLS tag device and providing the extracted location information to a client, and transmitting an alarm signal to the client, if it is determined that the emergency signal has been received or the location information deviates from a predetermined scope.

Abstract: A method and apparatus for transferring data. First data is transferred in a first direction on a surface of a selected magnetic disk in a plurality of magnetic disks using a first actuator assembly. Second data is transferred in a second direction on the surface of the selected magnetic disk in the plurality of magnetic disks using a second actuator assembly, while the first data is being transferred in the first direction by the first actuator assembly.

Abstract: A method may include receiving a first selection via a user interface comprising a hardware configuration for a simulated computer storage system, the hardware configuration including a plurality of hardware components. The method may also include receiving a second selection via the user interface comprising a storage configuration for the plurality of hardware components of the simulated computer storage system. Further, the method may include creating a storage configuration template utilizing the storage configuration. Additionally, the method may include associating the plurality of hardware components of the simulated computer storage system with the storage configuration template. Further, the method may include storing the plurality of hardware components of the simulated computer storage system and the associated storage configuration template.

Abstract: Described embodiments provide a method and system for signal compensation in a SERDES communication system that includes monitoring the quality of a data signal after passing through a transmission channel. The quality of the data signal is monitored with at least one of a BER calculation algorithm and a received eye quality monitoring algorithm. Variations in channel length of the transmission channel are compensated for by i) adjusting a length of transmission line delay of the data signal from the transmission channel, ii) comparing the data signal quality with a threshold for the adjusted data signal; and iii) repeating i) and ii) until the data signal quality meets the threshold.

Abstract: The present invention is a programmable QC LDPC encoder for encoding user data. The encoder may be configurable for implementation with a read channel. The encoder may include a plurality of barrel shifter circuits. The barrel shifter circuits are configured for generating a plurality of parity bits based on interleaved user bits received by the encoder. The barrel shifter circuits are further configured for outputting the parity bits. The encoder may further include an encoder interleaver memory. The encoder interleaver memory may be communicatively coupled with the barrel shifter circuits and may receive the parity bits output from the barrel shifter circuits. The encoder interleaver may be configured for interleaving the parity bits. Further, the encoder may be configured for outputting the interleaved parity bits to a multiplexer. The barrel shifter circuits may generate the plurality of parity bits via an encoding algorithm: p=u*GT.

Abstract: A mobile device is configured with electrical circuitry that causes the transmit channel electrical circuitry of the transmitter (Tx) of the mobile device to be electrically coupled to the receive channel electrical circuitry of the receiver (Rx) of the mobile device when one or more predetermined conditions occur. The electrical coupling of the transmit channel circuitry to the receive channel circuitry causes the Rx to be sufficiently damaged to render the mobile device nonoperational, thereby preventing further use of the mobile device. The one or more predetermined conditions correspond to conditions that indicate the mobile device has been lost or stolen and/or that an unauthorized user is attempting to use the mobile device in some manner.

Abstract: An optical-disc writer writes extrinsic data to an optical disc. Extrinsic data can be written as (i) embedded marks (e.g., pits and lands) located outside the conventional readable area of a disc and/or (ii) alternative marks, such as surface marks located on a surface of the disc. In an optical-disc player having a disc-reading subsystem and a read controller, the disc-reading subsystem reads and relays the extrinsic data to the read controller, which controls the operations of the player based on the extrinsic data. For example, the writer prints extrinsic data, e.g., a barcode, on the surface of a software installation disc. The disc is inserted in the player and installation is commenced. The read controller instructs the disc-reading subsystem to read the extrinsic information. If the read controller determines that the extrinsic data was successfully read, then installation proceeds; otherwise, installation is halted.