Abstract: A method for training an electronic memory may include receiving a first delay value and a second delay value. The first delay value and the second delay value may be associated with a first data strobe indicating when to sample data on a first memory lane of the electronic memory. The method may also include determining a difference between the first delay value and the second delay value. The method may further include receiving a third delay value associated with a second data strobe indicating when to sample data on a second memory lane of the electronic memory. The method may also include determining a fourth delay value for the second memory lane of the electronic memory utilizing the third delay value and the determined difference between the first delay value and the second delay value.

Abstract: A circuit breaker is disclosed, wherein the circuit breaker according to an exemplary embodiment of the present disclosure includes a permanent magnet rotatably hinged to a yoke, and wherein the permanent magnet is changed in magnetic path direction thereof by rotation to set up a sensitivity current, whereby a defect ratio of product is minimized.

Abstract: A communication gateway apparatus for a substation automation system, the gateway includes a VERSA Module Eurocard (VME) bus to provide a data communication path, a Peripheral Component Interconnect (PCI)-VME module connected to the VME bus for communication and having a PCI-VME bus bridge circuit to transfer data of the VME bus to a PCI bus or data of the PCI bus to the VME bus, and a plurality of input/output modules connected to the VME bus for communication.

Abstract: Disclosed is a temperature estimation apparatus and a method in thermocoupler input module of PLC, wherein the estimation according to the present invention is performed in such a manner that an analogue signal corresponding to a thermo-electromotive force is converted to a digital data, and the estimation is performed using a predetermined temperature estimation function corresponding to the thermo-electromotive force converted to the digital data.

Abstract: An apparatus configured to process a digital video signal comprising an input circuit, a processing circuit and an encoder circuit. The input circuit may be configured to present a digital video signal comprising a plurality of frames. The processing circuit may be configured to detect scene changes in the digital video signal by analyzing (i) a current one of the plurality of frames and (ii) two or more other frames. The encoder circuit may be configured to generate an encoded signal in response to the digital video signal and the scene changes. The two or more other frames may comprise (i) a first window of frames that are processed before the current frame and (ii) a second window of frames that are processed after the current frame. The processing circuit may also detect the scene changes by analyzing changes between the first window and the second window.

Abstract: A method of automatic luminance-chrominance delay compensation is disclosed. The method generally includes the steps of (A) generating an intermediate signal by processing a video signal such as to enhance a plurality of edges in a picture within the video signal, the picture having a luminance component and a chrominance component temporally separated from each other by an actual delay, (B) identifying an estimated delay between the luminance component and the chrominance component by correlating the luminance component in the intermediate signal to the chrominance component in the intermediate signal at a plurality of relative delays and (C) compensating for the actual delay by delaying one of either (i) the luminance component and (ii) the chrominance component by the estimated delay.

Abstract: Lighting apparatus and structures are described that are adapted for installation in housings. The housings can be pre-existing ones, such as those installed for high-intensity discharge (HID) or other types of lighting. The lighting apparatus can include a light unit (e.g., luminaire) with desired type of light source(s), for example, an array of LEDs. The apparatus can include structures that are adapted for use with the housings such that installation of a light unit requires a minimum of user effort and time. Such lighting apparatus, and related installation methods, can accordingly provide for high-efficiency lighting. Related assembly and installation techniques are also described.

Abstract: Described embodiments provide a memory system including a plurality of addressable memory arrays. Data in the arrays is accessed by receiving a logical address of data in the addressable memory array and computing a hash value based on at least a part of the logical address. One of the addressable memory arrays is selected based on the hash value. Data in the selected addressable memory array is accessed using a physical address based on at least part of the logical address not used to compute the hash value. The hash value is generated by a hash function to provide essentially random selection of each of the addressable memory arrays.

Abstract: Apparatus and methods for improved efficiency in accessing meta-data in a storage controller of a virtualized storage system. Features and aspects hereof walk/retrieve meta-data for one or more other I/O requests when retrieving meta-data for a first I/O request. The meta-data may include mapping information for mapping logical addresses of the virtual volume. Meta-data may also include meta-data associated with higher level, enhanced data services provide by or in conjunction with the storage system. Enhanced data services may include features for synchronous mirroring of a volume and/or management of time-based snapshots of the content of a virtual volume.

Abstract: A voltage translator circuit includes an input stage adapted for receiving an input signal referenced to a first voltage supply, a first latch circuit adapted for connection with a second voltage supply and operative to at least temporarily store a logic state of the input signal, and a voltage clamp coupled between the input stage and the first latch circuit. The voltage clamp is operative to set a maximum voltage across the input stage to a prescribed level. The voltage translator circuit generates a first output signal at a first output formed at a junction between the first latch circuit and the voltage clamp. A second latch circuit is connected to the first output in a feedback configuration. The second latch circuit is operative to retain a logical state of the first output signal as a function of at least a first control signal supplied to the second latch circuit regardless of a state of the first voltage supply.

Abstract: A circuit breaker includes a main case; a switching mechanism accommodated in the main case, and having a mechanical part for opening and closing a circuit; a trip mechanism configured to trigger the switching mechanism to a circuit interrupting position upon detection of an abnormal current on a circuit; and an external device detachably mounted to the main case, wherein the circuit breaker includes an interrupting means configured to interrupt the switching mechanism by contacting at least a part of the external device when the external device is mounted to the main case.

Abstract: In one embodiment of a header-compression method, a timestamp value is divided by a stride value using a plurality of binary-shift operations corresponding to a Taylor expansion series of the reciprocal stride value in a base of ½. When the division-logic circuitry of an arithmetic logic unit in the corresponding communication device is not designed to handle operands that can accommodate the length of the timestamp and/or stride values, the header-compression method can advantageously be used to improve the speed and efficiency of timestamp compression in communication devices.

Abstract: In one embodiment of a header-compression method, a 32-bit timestamp value is divided by a 16- or 8-bit stride value using a plurality of 16/8-bit division operations, each performed using a corresponding hardware instruction issued to an arithmetic logic unit (ALU) of the corresponding communication device, such as an access terminal or a base station of a communication system. When specialized 32/16-bit and/or 32/8-bit division-logic circuitry is not available in the ALU, embodiments of the header-compression method can advantageously be used to improve the speed and efficiency of timestamp compression in communication devices.

Abstract: An electronic device package includes first and second electrodes of a package substrate. The first electrode has fingers formed from a first metal level and is configured to operate at a first DC potential. The second electrode has fingers formed from the first metal level interdigitated with the fingers of the first electrode. A via conductively connects the second electrode to a second metal level. The second metal level is configured to operate at a second DC potential. The first and second DC potentials are thereby capacitively coupled through the interdigitated electrodes.

Abstract: A lighting apparatus having a base member and a directional member are shown and described. The base member includes a first surface having a plurality of reflective elements extending therefrom. The base member also including a plurality of openings arranged in a pattern. Each openings is configured to receive a respective light source. The directional member has a portion of a reflective surface positioned relative to at least one opening to reflect light radiating from a lighting source disposed within the opening towards a portion of at least one of the reflective elements extending from the base member.

Abstract: A circuit breaker having an arc extinguishing mechanism includes a plurality of grids disposed in a longitudinal direction, each having protruding portions at both ends thereof so as to define a space therebetween, a fixing portion to support the grids, insulating plates fixed to both sides of the grids, a stator located below the grids, the stator including an arc runner and a stationary contact disposed at an upper side of the arc runner, and a mover contactable with or separated from the stationary contact with moving up and down within the space, wherein an interval between the insulating plates within the space is shorter than a width of the mover.

Abstract: An apparatus and method are provided in various illustrative embodiments for an integrated circuit chip that provides a fast, compact, and cryptographically strong random number generator. In one illustrative embodiment, an apparatus includes an initial random source, and a post-processing block in communicative connection with the initial random source. The post-processing block is configured to receive signals from the initial random source, to apply one or more finite field operations to the signals to generate an output, and to provide an output signal based on the output via an output channel, in this illustrative embodiment.

Abstract: In described embodiments, turn-on time for active portions of an Energy Efficient Ethernet (EEE) device is improved by storing energy in a corresponding capacitor bank through a bidirectional device from a certain node in the device during an active state, continuing to store the energy when the device enters a Low Power Idle (LPI) state, and then allowing the energy to return to the node through the bidirectional device when the device returns to an active state. During active mode, the bidirectional device controls the capacitor bank so as to charge relatively slowly to store energy, and when the device transitions to LPI, the charge is maintained in the capacitor bank. When the device returns to the active state, the bidirectional device allows the capacitor bank to discharge relatively rapidly to the node, thereby improving the turn-on time of the circuit elements coupled to the node.

Abstract: A method may include defining an interface class including a static member having an implementation pointer. The method may also include loading a main code segment including a stub implementation of the interface class. Additionally, the method may include instantiating the stub implementation of the interface class to provide a stub implementation object. The stub implementation of the interface class may include a first constructor configured to set the implementation pointer to the stub implementation object. Further, the method may include loading a dynamic library including a real implementation of the interface class. Still further, the method may include instantiating the real implementation of the interface class to provide a real implementation object. The real implementation of the interface class may include a second constructor configured to set the implementation pointer to the real implementation object.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is disclosed that includes a first data detection circuit that applies a phase dependent data detection algorithm to a data set such that a first output of the first data detection circuit varies depending upon a phase of the data set presented to the first data detection circuit. A first phase of the data set is presented to the first data detection circuit. The circuits further include a decoder circuit that applies a decoding algorithm to the first output to yield a decoded output, and a phase shift circuit that phase shifts the decoded output such that a second phase of the data set is provided as a phase shifted output.