Abstract: A foldable element support made from planar sheet of material that can be formed by folding into a support for positioning and securing a refractor lens to a luminaire housing. The foldable element support is a planar sheet that has a central base having a central opening, a plurality of foldable securing arms formed into the central base for attaching the support to a luminaire housing, and a plurality of peripherally-arranged support flanges for supporting and positioning the upper rim of the refractor lens in proximity to the luminaire housing. The folded support can be manipulated into the folded configuration by hand, with hand tools, or by a machine.

Abstract: A method and computer program product for associating timing violations with critical structures in an integrated circuit design include steps of: (a) receiving as input an integrated circuit design; (b) identifying a critical structure in the integrated circuit design; and (c) generating as output a script for a static timing analysis tool that includes a timing check for a path having a start point at an input of the critical structure and an end point at an output of the critical structure.

Abstract: A method of time division multiplexing for a forward data packet channel includes encoding parallel data sub-packets into parallel streams of turbo codes; interleaving each of the parallel streams of turbo codes to generate parallel streams of quasi-complementary turbo codes; modulating the parallel streams of quasi-complementary turbo codes to generate parallel streams of modulated data symbols; and multiplexing the parallel streams of modulated data symbols by one of multiplexing and non-complete puncturing to generate a single stream of modulation symbols.

Abstract: An electrostatic discharge protection circuit adapted to reduce an electrostatic discharge event on a line of an integrated circuit. The protection circuit includes an NMOS transistor having a source contact that is electrically connected to the line. A drain contact is electrically connected to a logical low voltage, and a gate contact is also electrically connected to the logical low voltage, through a resistor. A substrate bias pump is electrically connected to a back gate of the NMOS transistor, where the bias pump provides a steady state direct current negative bias during normal operation of the integrated circuit when there is no electrostatic discharge event.

Abstract: The present invention is directed to a method of identifying test devices having excessive leakage current and also includes computer program products that enable the same. The method obtaining background test data using a test routine to measure the leakage current for a set of test devices as a function of a parameter associated with device speed for the device under test. From the test data, a leakage threshold function is defined that correlates leakage current with the parameter associated with device speed. The test routine and the leakage threshold function are then input into an automated testing apparatus configured to execute the test on production or other devices. Devices are tested to determine leakage current over a range of parameter values associated with device speed. The devices are then screened using the leakage threshold function to determine the status of the device.

Abstract: An improved Content Addressable Memory (CAM) architecture and method for operating the same is provided herein. The improved CAM architecture may generally include an array of memory cells arranged into rows and columns, where each row includes a number of memory cells configured for storing one word. In particular, the number of memory cells may be coupled to a plurality of local match lines which, when combined through a hierarchy of two or more logic gates, form a match line signal for the entire word. Dynamic logic is used within a compare portion of each memory cell to reduce the occurrence of functional failures. In addition, the improved method for operating the CAM reduces power consumption and peak current, and improves timing, by eliminating the need to restore the match line voltage to a preset voltage level before each new compare operation.

Abstract: A electronic design automation tool, apparatus, method, and program product by which design requirements for an intended semiconductor product and the resource definitions of a semiconductor platform are input. From the design requirements and the resource definitions, parameters specific to clocking are derived, e.g., clock property information, clock domain crossing information, and clock relationship specification. The tool and method embodied therein validates the clocking parameters of the design requirements with the resource definitions and invokes errors if the parameters are not realizable. Once the desired clocking parameters are consistent with the actual clocking parameters, correct physical optimization constraints and timing constraints are generated for the clocks. An iterative process can achieve correct and minimal clocking constraints.

Abstract: A networking/communication chip having a receiving buffer or FIFO whereby it receives data from a data source across a network and transfers the data to a host system. The memory in the host system acts as a logical extension of the receiving buffer in the chip; in this way, the host system controls the flow of data from the source, rather than the control flow being based on the capacity of the receiving buffer in the networking/communication chip. The networking/communication chip may be a controller, such as a 10 Gigabit Ethernet controller, wherein data received from the source in one protocol is transformed to a second protocol input to the host. If either or both the networking/communication chip or the host system is/are made of FPGAs, it/they can be reprogrammed to disable the flow control in the networking/communication chip and enable flow control in the host system. Data flow is enhanced because memory in the host system typically is much larger than memory in the networking/communication chip.

Abstract: The present invention provides a method for converting a netlist of an integrated circuit from a first library to a second library. The first library may include logic cells AND, OR and NOT, and the second library may include logic cells NAND and NOR. The method includes steps as follows. Logic cells of the netlist are topologically sorted from outputs to inputs. AND and OR cells of the netlist are replaced with NOT, NAND and NOR cells. Simplification of the netlist is performed in a topological order.

Abstract: When used as a test data generator, CDR internal structures may be applied to generate drift conditions in the test data. For example, a finite state machine phase shifts a clock signal, over time, driving the test data generator thereby producing a drift condition on the test data. Once the test is completed, one of the other CDRs may be used as a tester to similarly generate test data for the first CDR. CDRs may be configured in pairs for this purpose so that one may be used to test the other.

Abstract: A universal interface circuit and an associated method are provided that can supply a computer logic circuit, such as the components mounted upon an adapter card, with first and second inputs having first and second predetermined voltage levels, respectively, based upon power drawn from both first and second supply voltages. The interface circuit typically includes a first power supply circuit for providing the first input having the first predetermined voltage level in response to the first supply voltage. Additionally, the interface surface includes a regulator for generating an output having the second predetermined voltage level in response to the first supply voltage. The interface circuit further includes a second power supply circuit for providing an output that also has the second predetermined voltage level, albeit in response to the second supply voltage.

Abstract: A method for communicating between a first bus and a second bus is disclosed. The method generally includes the steps of (A) recognizing a read operation code in a read frame (i) received from the first bus and (ii) communicated with a first-bus protocol, (B) initiating a read transaction on the second bus using a second-bus protocol different than the first-bus protocol, wherein the initiating occurs earlier than a turn around time in the first-bus protocol that provides a plurality of bit times to respond to the read operation code and (C) transmitting read data received from the second bus on the first bus immediately after the turn around time.

Abstract: A method of determining whether voltage from an aggressor net exceeds a voltage threshold on a victim net design in an integrated circuit design. Probabilistic noise from the aggressor net on the victim net is calculated. The probabilistic noise is checked against the voltage threshold, and the victim net design is passed when the probabilistic noise does not exceed the voltage threshold. When the probabilistic noise does exceed the threshold, then an effective noise at a desired mean time to failure is computed, and the effective noise is checked against the voltage threshold. The victim net design is passed when the effective noise does not exceed the voltage threshold, and failed when the effective noise does exceed the threshold.

Abstract: The present invention provides a system and method for electrostatic discharge (ESD) testing. The system includes a circuit that has a switch coupled to an input/output (I/O) circuit of a device under test (DUT), a charge source coupled to the switch, and a control circuit coupled to the switch, wherein the control circuit turns on the switch to discharge an ESD current from the charge source to the I/O circuit, and wherein the circuit is integrated into the DUT. According to the system and method disclosed herein, the system provides on-chip ESD testing of a DUT without requiring expensive and specialized test equipment.

Abstract: Disclosed is a SCSI target device simulator consisting of a personal computer, a SCSI host adapter board, and simulator software. The SCSI target device simulator is employed to test SCSI host adapter systems by simulating multiple SCSI target devices for test purposes. The simulated SCSI target devices may be configured to imitate a wide variety of different SCSI target device types, with an equally wide variety of configuration settings within a single SCSI target device type. A user may quickly create and change simulated SCSI target devices for a test system. The SCSI target device simulator may also be configured so that the simulated SCSI target devices respond in a specified manner to SCSI commands and SCSI task management commands. Controlling the simulated SCSI target device responses to SCSI commands and SCSI task management commands allows a user to easily configure and test a SCSI host adapter device for specific operational scenarios.

Abstract: The present invention provides a safe method for upgrading firmware code for optical disk products without corrupting firmware even if an abnormality occurs during a upgrading a firmware process. A nonvolatile memory device of the present invention may store a boot system image and an application ware image separately. End users may update the application ware image by executing an upgraded application program. However the boot system image stored in the nonvolatile memory device may not be modified at any event and it may be used to restore the optical disk product from a system failure caused by a corrupted firmware.

Abstract: A pin-based memory power modeling method using arc-based characterization includes steps as follows. All power arcs of a memory model are identified and characterized. A power arc is selected from the identified and characterized power arcs. Output bus switching power is computed by removing overlapping power using the selected power arc, and a temporary value for various input ramp times and output loads is derived. Output pin power for the selected power arc is calculated using the temporary value and a ratio of a number of output bits switching over an entire bus width. Switching power for the selected power arc is calculated by a power estimation tool based on port activity and an input intrinsic power value.

Abstract: A method for performing post-optical proximity correction (OPC) multi layer overlay quality inspection includes the steps of generating a virtual target mask for a first mask and a second mask overlay using design rules at least partially defining the relationship between the first mask and the second mask; creating a composite aerial image representing a first mask image formed from the first mask and a second mask image formed by the second mask by performing imaging of the first mask and the second mask and overlaying the second mask image onto the first mask image; generating an overlay image map of the composite aerial image using the design rules at least partially defining the relationship between the first mask and the second mask; and comparing the overlay image map area and the virtual target mask area.

Abstract: A circuit which facilitates TDF testing without having to purchase expensive new test equipment, such as a new test platform that is capable of supporting test frequencies well beyond the current 200 MHz limitation. A solution to current TDF testing problems by adding circuitry to the device-under-test (DUT) that is configured to receive two reference clock signals from automated test equipment (ATE), i.e. conventional ATE which does not provide test frequencies beyond 200 Mhz, and create two high-speed clock pulses that serve as the launch and capture clocks for the TDF test sequence on the DUT.

Abstract: A system and method for packaging a command string in an offline mode into a script, transmitting the script, and using a controller to read the script and send commands and data to an individual device attached to the controller. The script may contain a header and one or more action and action payloads. When the script is interpreted by the controller, various commands and data may be passed directly to the individual device. Such a system may be useful for performing low level commands on the device, including loading firmware.