Abstract: A method of forming a metal gate in a wafer. PolySi1-xGex and polysilicon are used to form a tapered groove. Gate oxide, PolySi1-xGex, and polysilicon is deposited on a wafer. A resist pattern is formed. A portion of the polysilicon, PolySi1-xGex, and gate oxide is removed to provide a tapered profile. The resist is removed; a dielectric liner is deposited, and then at least a portion of the dielectric liner is removed, thereby exposing the polysilicon and leaving the dielectric liner in contact with the polysilicon, PolySi1-xGex, and gate oxide. A dielectric is deposited, and a portion is removed thereby exposing the polysilicon. The polysilicon, PolySi1-xGex, and gate oxide is removed from inside the dielectric liner, thereby leaving a tapered gate groove. Metal is then deposited in the groove.

Abstract: An improvement to a key equation solver block for a BCH decoder, where the key equation solver block having a number of multiplier units specified by X, where: t*(7*t?1)/(codeword_len?3)?X<(t+1), where t is a number of transmission errors for the key equation solver block to correct, and codeword_len is a length of a transmitted codeword to be decoded by the BCH decoder.

Abstract: A data-processing system and method include a processor core associated with a cache controller. A plurality of cached memory components is associated with the processor core and the cache controller. A cached processor is provided, which supports a plurality of varying sizes of instruction and data cache, wherein the cached processor comprises a processor core separated from the cache controller and the plurality of cached memory components, thereby permitted the cached processor to support varying sizes of cache memory in a flexible memory arrangement thereof.

Abstract: The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.

Abstract: A method and system for selectively identifying reliability risk die based on characteristics of local regions on a wafer by computing particle sensitive yield and using the particle sensitive yield to identify reliability risk die. Specifically, a bin characteristics database which identifies hard and soft bins that are sensitive to different failure mechanisms is maintained, and the bin characteristics database is used to compute particle sensitive yield. It is determined whether the particle sensitive yield of the local region around the current die is less than a pre-set threshold, and the die is downgraded if the particle sensitive yield of the local region around the current die is less than the pre-set threshold. If the particle sensitive yield of the local region around the current die is not less than the pre-set threshold, the die is not downgraded.

Abstract: A method and firmware for avoiding timing violations resulting from process defects in a backfilled metal layer of an integrated circuit includes steps of receiving as input timing information for an integrated circuit design including at least one metal layer and a plurality of signal wires and dummy metal wires in the metal layer, finding at least one of a setup time and a hold time for each signal wire in the metal layer from the timing information, identifying a timing-critical signal wire from at least one of the setup time and the hold time for one of the signal wires that would produce a timing violation in the signal wire when the signal wire is shorted to a dummy metal wire by a process defect in the metal layer, calculating at least one of a wire width, a fracture interval, and a spacing for modifying the dummy metal wire to avoid the timing violation in the timing-critical signal wire, and generating as output at least one of the wire width and the fracture interval for the dummy metal wire.

Abstract: An electromagnetic interference (EMI) gasket for an electronic module comprises a valley feature formed on one side of an EMI gasket and a crown feature formed on the other side of the EMI gasket in order to complement the valley. One or more EMI gaskets are used to construct a shield across the opening of a module cage or rack. Each gasket forms a link in a series of modules, in order to complete a seal across the opening in the cage. A perpendicular pressure forces the module gaskets to center and align evenly as the crown and valley of the opposite features nest together. The modules can be then pressed together and the overlap of the crown and valley acts to center the alignment and create a pressure for satisfactory EMI grounding and the reduction of EMI leakage.

Abstract: A multiple-processor system and boot procedure are provided. The system includes an integrated circuit having first and second embedded processors. A volatile memory and a non-volatile memory are shared by the first and second processors. The non-volatile memory includes a set of boot load instructions executable by the first and second processors.

Abstract: A process and apparatus are provided for tiling objects, such as design memories, in one or more respective object locations in a layout pattern. For each object, the following steps are performed recursively based on a comparison of at least one of a capacity and a width of the object and that of the respective object location: (1) do nothing; (2) reconfigure the object to have a different capacity and/or width; and (3) split the object into two or more separate objects. The recursion is repeated for each reconfigured object and each separated object.

Abstract: An automated system for validating Peripheral Component Interconnect (PCI) bus adapters or PCI-X bus adapters has a computer, motherboard, a PCI-X bus and isolated test slot for operatively coupling a PCI/PCI adapter under test through the PCI-X bus to the motherboard. The isolated test slot is adapted and arranged to minimize degradation of data flow on the PCI-X bus such that a PCI-X adapter, mounted in the isolated test slot, can negotiate a required operating rate greater than PCI operating rates. It can be configured as a low profile slot in a low profile computer system, such as a 2U low profile system. A method for validating the PCI/PCI-X bus adapters comprises operatively coupling the bus adapter under test to the motherboard, negotiating to the required operating rate and testing the functionality of the adapter. The operating rate of the bus adapter can be verified to ensure the PCI/PCI-X bus adapters are tested at required PCI/PC-X rates.

Abstract: A method for forming a feature in a substrate, where residue within the feature can be easily removed. An upper sidewall portion of the feature is formed, where the upper sidewall portion forms a void in the substrate. The upper sidewall portion has an upper sidewall angle. A lower sidewall portion of the feature is formed, where the lower sidewall portion forms a void in the substrate. The lower sidewall portion has a lower sidewall angle. The upper sidewall angle of the upper sidewall portion is shallower than the lower sidewall angle of the lower sidewall portion. By forming the feature with a shallower sidewall angle at the top of the feature, any debris within the feature is more susceptible to rinsing, etching, or other cleaning procedures, and thus the feature is more easily cleaned than standard features having relatively steeper sidewalls.

Abstract: An integrated circuit (IC) includes one or more inductors that have magnetic flux lines substantially parallel to a generally horizontal plane of the IC. The inductor is formed in a plurality of conductor layers separated by insulating layers of the IC. Regions of highest magnetic flux density of the inductor may preferably be located near the edge of the IC. Additionally, the inductor may preferably be segmented. The over-all inductance may preferably be controlled by turning on and off selected inductors or inductor segments.

Abstract: Method and apparatus for canceling an echo path by locating an active region thereof for subsequent application of a filter thereto. A plurality of far-end signals RIN(n) and a corresponding plurality of near-end signals SIN(n) are acquired. Correlation within the far-end and near-end signals RIN(n) and SIN(n) is removed and gain control applied to bring the corresponding ones of the far-end and near-end signals RIN(n) and SIN(n) to a uniform level. The plurality of far-end and near-end signals RIN(n) and SIN(n) are then stored in respective data blocks. The stored data blocks are subsequently processed together to determine a set of coefficients for a bank of adaptive filters. An energy estimate is computed for each one of the bank of adaptive filters and the location of the active region of the echo determined from the energy estimates.

Abstract: Methods and structure for standardized communication between a test operator, a host system, and an embedded system under test. Test program instructions are designed, written for, and executed on, an embedded system under test in accordance with standard API functions for message exchange. Still further, the invention provides for standards in the user interface to select a desired test, to start the test with defined parameters and to present reply and status information to the test operator. These user interactions are defined in a test configuration language of the present invention and preferably incorporated with the executable image file to define an integral test vehicle file. The present invention thereby reduces test sequence development time by providing standard API functions for message exchange between a host system test application and the system under test and provides for standardized user interaction in a flexible, easily maintained design language.

Abstract: An LDPC decoder that implements an iterative message-passing algorithm, where the improvement includes a pipeline architecture such that the decoder accumulates results for row operations during column operations, such that additional time and memory are not required to store results from the row operations beyond that required for the column operations.

Abstract: An architecture for a block cipher, where the architecture includes functional units that are logically reconfigurable so as to be able to both encrypt clear text into cipher text and decrypt cipher text into clear text using more than one block cipher mode based on at least one of advanced encryption standard and data encryption standard.

Abstract: A circuit for implementing elliptic curve and hyperelliptic curve encryption and decryption operations, having a read only memory with no more than about two kilobytes of accessible memory, containing first programming instructions. An arithmetic logic unit has access to second programming instructions that are resident in a gate-level program disposed in the arithmetic logic unit, and is operable to receive data from no more than one input FIFO register. A microcontroller has no more than about two thousand gates, and is adapted to read the first programming instructions from the read only memory, send control signals to the arithmetic logic unit, and receive flags from the arithmetic logic unit. The arithmetic unit reads the third programming instructions, selectively performs elliptic curve and hyperelliptic curve encryption and decryption operations on the data according to the second programming instructions and the microcontroller, and sends output to no more than one output FIFO register.

Abstract: A mask for use in a photolithographic process. The mask includes a plate or substrate having first and second opposite surfaces, a first image on the first surface of the substrate and a second image on the second surface of the substrate. When the mask is used in a photolithographic process, energy is reflected by the first image prior to entering the substrate and energy is reflected by the second image after passing through the substrate.

Abstract: The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.

Abstract: The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.