Abstract: A device generally having a memory manager and a direct memory access unit. The memory manager may be configured to (i) map a first picture from a video signal among a plurality of picture segments and (ii) generate a list associating each of the picture segments to a plurality of physical pages in a memory. The direct memory access unit may be configured to store the first picture among the physical pages according to the list and the mapping.

Abstract: A method of encoding a binary source message u, by calculating x:=Au, calculating y:=B?x, resolving the equation Dp=y for p, and incorporating u and p to produce an encoded binary message v, where A is a matrix formed only of permutation sub matrices, B? is a matrix formed only of circulant permutation sub matrices, and D is a matrix of the form D = ( T 0 ? 0 0 0 T ? 0 0 ? ? ? ? ? 0 0 ? T 0 I I ? I I ) where T is a two-diagonal, circulant sub matrix, and I is an identity sub matrix.

Abstract: The present invention provides a new approach and algorithm to optimize various design parameters in global routing. According to an exemplary aspect of the present invention, marked trees are first preprocessed. For every vertex incident to leaves, one may go through the list of its leaves, and if two leaves have the same mark one may leave only one of them. After that whether homeomorphism exists may be determined. The reason behind selecting such homeomorphic pairs is as follows: adding or removing a vertex of degree 2 as well as adding or removing a new leaf (variable) does not significantly modify routing (in this case all routing transformations are in essence splitting and merging routing trees). After the selection of applicable transformations, one may apply them to optimize design parameters.

Abstract: The present invention is directed to a method and system of intelligent dummy filling placement to reduce inter-layer capacitance caused by overlaps of dummy filling area on successive layers. The method and system treats each consecutive pair of layers together so as to minimize dummy filling overlaps between each layer. In particular, dummy fill features on each layer may be placed in a checkerboard pattern to avoid overlaps. As such, the present invention may eliminate large overlap area of the dummy patterns on consecutive layers by utilizing intelligent dummy filling placement.

Abstract: A deep n-well is formed beneath the area of a capacitor structure. The use of a deep n-well lessens the parasitic capacitance by placing a diode in series with the interlayer dielectric cap. The deep n-well also reduces substrate noise. Once the n-well is implanted and annealed, a cross hatch of shallow trench isolation is patterned over the n-well. The shallow trench isolation reduces and confines the inductively and/or capacitively coupled surface currents to small areas that are then isolated from the rest of the chip.

Abstract: An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a video input signal having a voltage. The second circuit may have a finite input resistance configured to generate a current in response to presenting the voltage across the finite input resistance. The third circuit may be configured to cancel the current by (i) generating the current in response to presenting the voltage across a replica resistor having a resistance similar to the finite input resistance and (ii) passing the current away from the apparatus.

Abstract: A method to validate data used in a design of a semiconductor product. The method includes (a) reading resources of an application set defining the semiconductor product in a partially fabricated state comprising fabrication layers up to and including a lowest conductive layer (b) reading a user specification that (i) is developed based upon the application set at the partially fabricated state and (ii) establishes at least one upper conductive layer added to the application set that completes the design of the semiconductor product, (c) allocating a new resource from the user specification to the design of the semiconductor product, said new resource having multiple parameters, (d) validating the allocation of the new resource against the resources of the application set and (e) propagating the allocation of the new resource and the parameters throughout a description of the semiconductor product.

Abstract: A method for responding to a particular drive being removed from a drive array, comprising the steps of (A) determining a maximum drive response time of the particular drive being removed from the drive array; (B) determining a duration of each of one or more commands needing completion; (C) if a particular one of the commands takes longer than the maximum drive response time, aborting the particular command and checking if the drive is physically present; and (D) if the command takes less than the maximum drive response time, completing the command.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate context information in response to one or more bins on a binary signal. The second circuit may be configured to generate the binary signal in response to (i) one or more input bits on a bitstream signal, and (ii) simultaneously performing in a single cycle (a) an arithmetic decode of the context information and (b) a renormalization of the context information.

Abstract: The present invention provides a comprehensive design environment defining a system architecture and methodology that may integrate interconnects, cores, ePLC, re-configurable processors and software into a manageable and predictable system designs that achieve on-time system IC design results meeting desired specifications and budgets. For example, an interscalable interconnect maybe provided that is scalable and isochronous capable. Additionally, an abstract language may be provided to be able to describe interconnecting core functions. Further, a self-programmable chip may be provided that, upon receiving a construct, it could program itself to achieve the desired functionality, such as through the use of on-chip knowledge and the like.

Abstract: A method for establishing standard cell power connections is disclosed. The method generally includes the steps of (A) calculating a power consumption of a plurality of logic cells receiving power directly from a power rail, (B) removing at least one excess via from a plurality of vias directly connecting the power rail to a power mesh in response to the power consumption and (C) routing a signal through an area where the at least one excess via was removed.

Abstract: A method of determining whether voltage from an aggressor net exceeds a voltage threshold on a victim net design in an integrated circuit design. Probabilistic noise from the aggressor net on the victim net is calculated. The probabilistic noise is checked against the voltage threshold, and the victim net design is passed when the probabilistic noise does not exceed the voltage threshold. When the probabilistic noise does exceed the threshold, then an effective noise at a desired mean time to failure is computed, and the effective noise is checked against the voltage threshold. The victim net design is passed when the effective noise does not exceed the voltage threshold, and failed when the effective noise does exceed the threshold.

Abstract: The invention provides a number of related methods which improve the test and analysis of integrated circuit devices. A first method of the invention provides a method for pausing on a SCAN based test. A second method of the invention provides a method for using stimulations and responses of a slown good device to increase fault coverage of patterns in a test flow. A third method of the invention provides a method to curve trace device buffers on an ATE.

Abstract: An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may include a plurality of first multiplexers and one or more second multiplexers configured to generate a first intermediate enable signal in response to (i) an input enable signal, (ii) a first clock signal operating at a first data rate and (iii) a plurality of first select signals. The plurality of first multiplexers each present an output to each of the one or more second multiplexers. The second circuit may be configured to generate a second intermediate enable signal in response to (i) the first intermediate enable signal, (ii) a second clock signal operating at a second data rate and (iii) a second select signal. The third circuit may be configured to generate a third intermediate enable signal in response to (i) the second intermediate enable signal, (ii) a control input signal and (iii) a third select signal. The third intermediate enable signal may be configured to control a read operation of a memory.

Abstract: The present invention is directed to a system, software system and method for manipulating multimedia broadcast presentations. Manipulating multimedia events offers users increased options in how they experience multimedia presentations. Thus increasing the overall multimedia experience and consequently user satisfaction. Utilization of the present invention allows the user to experience combinations of media previously unavailable. For example, in implementations of the present invention, users may option various combinations of audio and video; including the rate at which a user experiences the media. Further, the user may text search to find starting and stopping points for recording, viewing and pausing operations. The user play programming allows the user to customize how a single media, such as audio, is experienced.

Abstract: The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.

Abstract: Provided is a process for forming a barrier film to prevent resist poisoning in a semiconductor device by depositing a second nitrogen-free barrier layer on top of a first barrier layer containing nitrogen. A low-k dielectric layer is formed over the second barrier layer. This technique maintains the low electrical leakage characteristics of the first barrier layer and reduces nitrogen poisoning of a photoresist layer subsequently applied.

Abstract: A graphical profile map for integrated circuits on a substrate. The graphical profile map includes a depiction of die placement boundaries and shot placement boundaries for the integrated circuits on the substrate. Also included are integrated circuit property information contours, where the contours are not limited to either of the die placement boundaries or the shot placement boundaries. In this manner, three key pieces of information for the integrated circuits are presented, including integrated circuit property information, die placement, and shot placement. Because these three pieces of information are presented in a graphical form, it is much easier to interpret the information. For example, it is much easier to determine which shot and die placements have properties that are at risk, and which shot and die placements have adequate property profiles.

Abstract: An apparatus for locating failed disk drives on a disk array module when the disk-array module is removed from its enclosure is described.

Abstract: A methodology for generating scan based transition patterns (i.e., ATPG pattern generation for transition delay faults (“TDF”)) wherein when either a slow-to-rise (STR) or a slow-to-fall (STF) transition fault is detected, that specific fault is removed from a fault universe as well as its companion TDF, wherein the companion fault is a fault on the same node as the detected fault but has the opposite transition. In other words, if a slow-to-rise (STR) transition fault is detected, the slow-to-rise (STR) transition fault is removed from the fault universe as well as its corresponding slow-to-fall (STF) transition fault (and vise versa). By removing companion faults as well as those which are specifically detected, pattern generation run time is reduced as well as the total pattern count for the final delay test pattern.