Abstract: An apparatus comprising an integrated circuit having (i) a number of regions each pre-diffused and configured to be metal-programmed and (ii) a plurality of pins configured to connect the integrated circuit to a socket. A logic portion may be implemented on the integrated circuit (i) configured to implement integrated circuit operations and (ii) having one or more I/O connections and one or more supply connections. A first group of the pre-diffused regions are metal-programmed and coupled to said I/O connections. A second group of the pre-diffused regions are metal-programmed and coupled to the supply connections.

Abstract: A method for forming a feature in a substrate, where residue within the feature can be easily removed. An upper sidewall portion of the feature is formed, where the upper sidewall portion forms a void in the substrate. The upper sidewall portion has an upper sidewall angle. A lower sidewall portion of the feature is formed, where the lower sidewall portion forms a void in the substrate. The lower sidewall portion has a lower sidewall angle. The upper sidewall angle of the upper sidewall portion is shallower than the lower sidewall angle of the lower sidewall portion. By forming the feature with a shallower sidewall angle at the top of the feature, any debris within the feature is more susceptible to rinsing, etching, or other cleaning procedures, and thus the feature is more easily cleaned than standard features having relatively steeper sidewalls.

Abstract: An apparatus including a base layer of a platform application specific integrated circuit (ASIC), a mixed-signal function and a built-in self test (BIST) function. The base layer of the platform ASIC generally includes a plurality of pre-diffused regions disposed around a periphery of the platform ASIC. Each of the pre-diffused regions is generally configured to be metal-programmable. The mixed-signal function may include two or more sub-functions formed with a metal mask set placed over a first number of the plurality of pre-diffused regions. The BIST function may be formed with a metal mask set placed over a second number of the plurality of pre-diffused regions. The BIST function may be configured to test the mixed-signal function and present a digital signal indicating an operating condition of the mixed-signal function.

Abstract: Methods and apparatus for providing improving optical signal transmission results over standard mode fiber using a combination of negative chirp, low extinction ratio, and self-phase modulation transmission techniques in combination are described. The use of pre-transmission signal distortion in combinations with one or more of the other transmission techniques is also described. Pre-transmission signal distortion may be introduced by controlling a modulator with a large symmetric AC signal which causes the modulator to operation in a non-linear region or, alternatively, by using a relatively small non-symmetric AC signal to drive the modulator. Use of the small non-symmetric signal has the advantage of reduced power requirements. The pre-transmission distortion acts to counter some of the distortion introduced by the transmission of the signal over an optic fiber.

Abstract: The present invention provides methods and apparatus for accomplishing a phase shift lithography process using a off axis light to reduce the effect of zero order light to improve the process window for maskless phase shift lithography systems and methodologies. A lithography system is provided. The lithography system provided uses off axis light beams projected onto a mirror array configured to generate a phase shift optical image pattern. This pattern is projected onto a photoimageable layer formed on the target substrate to facilitate pattern transfer.

Abstract: A method for encoding quantization matrices comprising the steps of (A) signaling whether values of a luma quantization matrix are determined by either (i) a first set of custom values or (ii) a set of standardized default values, (B) transmitting the first set of custom values when the values of the luma quantization matrix are determined by the first set of custom values and (C) signaling whether values of a first chroma component quantization matrix are determined by either (i) a second set of custom values or (ii) the values of the luma quantization matrix.

Abstract: A built in self test circuit disposed within a memory matrix. Individual memory cells within the memory matrix are disposed into logical columns. The built in self test circuit has only one memory test controller, which is adapted to initiate test commands and receive test results. Transport controllers are uniquely paired with each one of the logical columns of memory cells. Each of the transport controllers is adapted to receive test commands from the memory test controller, test memory cells within the logical column as instructed by the test commands, receive test results from the logical column of memory cells, and provide the test results to the memory test controller. The transport controllers are also adapted to selectively operate in three different modes under control of the memory test controller.

Abstract: A circuit generally including a first module, a second module and a third module is disclosed. The first module may be configured to (i) generate a plurality of parsed residual blocks by parsing a plurality of 4×4 CAVLC (context-based adaptive variable length coding) residual blocks received in an input signal and (ii) generate a plurality of metric signals resulting from the parsing of the 4×4 CAVLC residual blocks. The second module configured to generate a plurality of scanning position signals based on the metric signals. The third module configured to generating an 8×8 CABAC (context-based adaptive binary arithmetic coding) residual block in an output signal by up-sampling the parsed residual blocks based on the scanning position signals.

Abstract: A method of routing an integrated circuit design includes steps of receiving as input at least a portion of an integrated circuit design including at least two separate routing rules assigned to the same net for routing the integrated circuit design, formulating a single combined routing rule as a function of content of each of the separate routing rules, and generating as output the combined routing rule and a routing rule assignment that assigns the combined routing rule to the net.

Abstract: A system and method for collecting and analyzing integrated circuit test vehicle test data by identifying various blocks of circuitry through at least two different intersecting test paths. In one embodiment, the process test circuits may be arranged in a matrix format and connected so that they may be tested along rows or columns. When a failure along a specific row and a specific column is identified, the process test circuit at the intersection may be identified as the failure point.

Abstract: Methods and structures for efficiently storing task file information for a significant number of SATA devices coupled to a SATA storage controller. A RAM memory within the SATA storage controller may store task file information for virtually any number of SATA devices coupled to a SAS communication domain. An arbiter and multiplexing logic is coupled to multiple client logic blocks or processes of the controller each operable to control one or more corresponding SATA devices. The arbiter and associated multiplexing logic grants each client process an opportunity to control its corresponding devices by retrieving saved state information from the task file RAM storage.

Abstract: The present invention is directed to a system, software system and method for effectively managing multimedia broadcast presentations. Effective multimedia broadcast data management offers users increased functionality in how they experience multimedia presentations, manage data and control hardware, such as a personal video recorder. Thus increasing the overall multimedia experience and consequently user satisfaction. Utilization of the present invention allows the user to experience combinations of media previously unavailable. For example, in implementations of the present invention, users may option various combinations of audio and video; including the rate at which a user experiences the media. Further, the user may text search to find starting and stopping points for recording, viewing and pausing operations. Additionally, in embodiments the present invention may be utilized to prioritize stored multimedia presentations.

Abstract: A transistor integration process provides a damascene method for the formation of gate electrodes and gate dielectric layers. An interlayer-dielectric film is deposited prior to the gate electrode formation to avoid the demanding gap fill requirements presented by adjacent gates. A trench is formed in the interlayer-dielectric film followed by the deposition of the gate material in the trench. This process avoids the potential for damage to high-k gate dielectric layers caused by high thermal cycles and also reduces or eliminates the problematic formation of voids in the dielectric layers filling the gaps between adjacent gates.

Abstract: A method of forming a metal gate in a wafer. PolySi1-xGex and polysilicon are used to form a tapered groove. Gate oxide, PolySi1-xGex, and polysilicon is deposited on a wafer. A resist pattern is formed. A portion of the polysilicon, PolySi1-xGex, and gate oxide is removed to provide a tapered profile. The resist is removed; a dielectric liner is deposited, and then at least a portion of the dielectric liner is removed, thereby exposing the polysilicon and leaving the dielectric liner in contact with the polysilicon, PolyS1-xGex, and gate oxide. A dielectric is deposited, and a portion is removed thereby exposing the polysilicon. The polysilicon, PolySi1-xGex, and gate oxide is removed from inside the dielectric liner, thereby leaving a tapered gate groove. Metal is then deposited in the groove.

Abstract: The present invention is a method and system for providing a complete validation of an initiator and target within bus architecture. A target's behavior may be controlled by an initiator. Control of the target may be through execution of initiator commands including vendor unique commands relating to desired characteristics for testing. The initiator's response to the target's behavior may be verified due to the handshaking communication protocol between a target and initiator. Additionally, by altering the behavior of the target to test initiator response, a target's behavior is also validated.

Abstract: A method and apparatus are provided for interfacing with a synchronous dynamic memory in which memory commands are provided to the memory. The memory is accessed in response to the memory commands. Read data is captured in a data capture circuit having a delay setting. The delay setting is updated in response to detection of a period of read inactivity of the memory.

Abstract: The present invention provides solid support media for use in oligomer synthesis, methods of producing the media, and methods of using the media. In some embodiments, the processes of the invention comprise (a) providing an organic phase comprising an olefin monomer, a cross-linker, a functionalizing reagent and an initiator; and (b) contacting the organic phase with an aqueous phase under conditions of time and temperature effective to form the polymeric bead.

Abstract: A method and apparatus for using and combining sub-frame processing and adaptive jitter-buffers for improved voice quality in voice-over-packet networks. Data is placed in a jitter buffer, where the data has a frame-length consisting of a plurality of samples. Some of the samples are placed in the DMA buffer, and some of the samples are placed in the back-up buffer. Samples are read out of the DMA buffer, and samples are moved from the back-up buffer to the DMA buffer.

Abstract: System and methods are disclosed for load balancing Input/Output (IO) commands to be executed by one or more disk drives from an array of disk drives. Systems and methods disclosed herein use one or more properties, such as disk drive RPM, disk drive cache, command queue lengths, real-time drive data, and head position to provide load balancing of Input/Output commands.

Abstract: One aspect of the present invention concerns a method for controlling the frequency of oscillation of a local clock signal comprising the steps of (A) generating the clock signal in response to a first control signal, (B) generating the first control signal in response to one of a plurality of adjustment signals selected in response to a second control signal and (C) generating the second control signal in response to a comparison between a local timestamp and an external timestamp.