Abstract: A system and method are disclosed for providing a gain control signal for a multilevel read signal. In one embodiment, maximum automatic gain control marks are periodically inserted amongst a series of data fields. The automatic gain control marks include a series of high level marks such that the maximum signal detected in the interior portion of each maximum automatic gain control mark is not reduced by intersymbol interference. Minimum automatic gain control marks are also periodically inserted amongst a series of data fields. The automatic gain control marks include a series of high level marks such that the maximum signal detected in the interior portion of each minimum automatic gain control mark is not reduced by intersymbol interference. In another embodiment, multilevel signals are encoded to facilitate automatic gain control. The effect of a plurality of candidate merge symbols on the residual running total power associated with a current data block is determined.

Abstract: Methods and structures within a SAS expander for testing SAS devices and other SAS expanders in the SAS domain. Testing devices and expanders in the domain by operations performed within a SAS expander in the domain relieves the burden of such processing in attached host systems and adds flexibility for scheduling processing for test operation of devices and expanders in the domain. In one aspect hereof, the testing may be performed by a master SAS expander configured in the domain. The SAS expander may initiate testing of devices following completion of the SAS discovery process. Testing may also be initiated in response to events in the SAS domain not typically detected by attached host systems.

Abstract: A method and computer program are disclosed for managing synchronous and asynchronous clock domain crossings that include steps of: (a) receiving as input an integrated circuit design; (b) identifying paths between synchronous clock domains and paths between asynchronous clock domains in the integrated circuit design; and (c) if a path between synchronous clock domains is defined as a false path in the integrated circuit design, then reporting a fatal violation.

Abstract: The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.

Abstract: An instrument and method for suturing wound closures is provided having a handle, shaft and suture engagement mechanism. The instrument provides for multiple placements or “bites” of suture in tissues to enable a wide variety of suturing techniques, including the ability to “run” a suture. The instrument further facilitates suture knot tying. The method of this instrument provides for rapid and effective remote suture placement and knot tying.

Abstract: An integrated circuit is provided that includes an execution engine and a memory controller. The execution engine is clocked at a first rate and the memory controller is clocked at a second rate that is less than the first rate. Pins on the integrated circuit can transfer data to and from the integrated circuit on both the rising and falling edges of a second clock transitioning at the second clock rate. The integrated circuit is preferably packaged using a lead frame and wire bonds extending from pads on the integrated circuit to corresponding leads. The leads are secured to trace conductors on a surface of a printed circuit board. The board contains no more than two conductive layers separated by a dielectric layer.

Abstract: An apparatus, computer program product, and method for preventing piracy in combined hardware/software products, and specifically in RAID storage systems is disclosed. In a preferred embodiment of the present invention, when a hardware device (a disk controller, in a preferred embodiment) is initialized, the device executes firmware that directs it to write a signature to a storage location (scratchpad register) in the device, where the signature corresponds to a set of product features authorized for use with the hardware device. When application code executing on the host computer system attempts to access a feature (e.g., through device driver code), the stored signature is read from the hardware device. The code implementing the feature is allowed to execute only if the signature that is read from the hardware device matches a feature level of the product in which that feature is authorized.

Abstract: An apparatus comprising an analysis block, a graphic user interface and a memory circuit. The analysis block may be configured to generate debug information in response to (i) a command input, (ii) one or more simulation outputs, and (iii) one or more compiler outputs. The graphic user interface may be configured (i) to present the command input in response to one or more user input parameters and (ii) to display the debug information. The memory circuit may be configured to store the one or more simulation outputs and said one or more compiler outputs.

Abstract: Where links between a port module and plural switch fabric slices are of various lengths, a cell is transmitted from the port module to a switch fabric slice in response to a grant. The transmission is delayed by an amount based on a link round trip delay (RTD) value for the corresponding link between the port module and the switch fabric slice, and a predetermined global delay value. As a result of this delay, the cell arrives at the switch fabric slice at a fixed number of cell times (equal to the global delay value) after issuance of the grant, independent of any link lengths.

Abstract: The present invention provides disk coercion by generating coercion percentages or values that can be used to coerce various disks according to each disk's particular labeled size or capacity. In one embodiment, a disk size is received and a base coercion scaling factor is provided such that the received disk size is coerced according to the base coercion scaling factor if the labeled disk capacity is below a disk size threshold. The coercion scaling factor increases for labeled disk capacity above the disk threshold. If the labeled disk capacity is above the disk size threshold, then a coercion scaling factor is provided according to the rate of increase of coercion scaling factors and the labeled disk capacity.

Abstract: An integrated circuit, or portion thereof, such as a CMOS device, includes an epitaxially grown dielectric on a silicon carbide base. The epitaxially grown dielectric forms a gate dielectric and the silicon carbide base serves as a channel region for the CMOS device. In various embodiments, the epitaxially grown dielectric may be a crystalline carbon or carbon-containing film.

Abstract: A method for motion estimating. The method generally includes the steps of (A) generating a first interpolated block having a sub-pixel resolution in response to a first interpolation process operating on a reference block of a reference frame of a video signal having an integer pixel resolution, (B) generating a motion vector in response to the first interpolated block and a current block of a current frame of the video signal having the integer pixel resolution and (C) generating a second interpolated block having the sub-pixel resolution in response to a second interpolation process operating on the reference block.

Abstract: A method of avoiding substrate noise in an integrated circuit includes steps of receiving as input an integrated circuit design that includes at least a portion of a block for placement and routing on a substrate and an outer boundary of the block. An end cell is selected from a set of end cells for terminating the block in an outer area that extends from the outer boundary to an end cell boundary outside the block. The selected end cell is placed in the outer area to isolate the block electrically from the substrate.

Abstract: A system and method for testing a device with multiple interfaces by generating a predetermined data pattern within the device, transmitting the pattern to a test analyzer, generating a second predetermined data pattern within the test analyzer, and simultaneously transmitting the second test pattern to the device where the second test pattern is verified. The first and second test patterns may be the same or different, depending on the application. Further, the transmit and receive paths may be tested separately and independently in addition to simultaneously.

Abstract: A method of enabling CRPR in an ETM. In an exemplary embodiment, the method includes locating a plurality of clocks defined within a core. The method may also include determining if one of the plurality of clocks are clocking data both within the core and outside of the core. A CRPR clock for an output pin of a last cell in a clock path common to an internal register clock pin and one of the plurality of clocks clocking data clocking data both within the core and outside of the core may be defined. A static timing analysis tool may be employed to calculate the CRPR from the CRPR clock.

Abstract: A scan chain partition includes a serial input coupled to a scan input signal pin of a module under test. A plurality of scan sub-chains is coupled to the serial input. A scan sub-chain output multiplexer is coupled to the plurality of scan sub-chains for sequentially selecting only one of the scan sub-chains in response to a scan sub-chain control signal. A scan sub-chain controller generates the scan sub-chain control signal and gates a scan clock signal to only a scan clock input of the selected scan sub-chain.

Abstract: An apparatus includes a first semiconductor die and at least one further semiconductor die. A substrate is attached to the first die and the further die and has an electrical interconnect pattern that interconnects contacts on the first die with respective contacts on the further die. Features of the interconnect pattern have positions on the substrate with smaller tolerances relative to positions of the contacts on the first die than to positions of the contacts on the further die.

Abstract: A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selective to wet chemicals used to remove the dummy gate oxide thereby preventing undercut in the spacer region. The method is aimed at making the metal gate electrode technology a feasible technology with maximum compatibility with the existing fabrication environment for multiple generations of CMOS transistors, including those belonging to the 65 nm, 45 nm and 25 nm technology nodes, that are being used in analog, digital or mixed signal integrated circuit for various applications such as communication, entertainment, education and security products.