Abstract: A plate to plate capacitor has a first plate, a second plate, and an insulating medium separating the first plate from the second plate. The first plate and the second plate are adapted and arranged to form an interlaced structure in which multiple capacitance surface areas in different planes, such as horizontal and vertical, are provided between said first and second plates. The plate to plate capacitor can be formed as a stack of layers in which one or more alternating first and third insulating layers each have first and second conductive lines configured therein and in which one or more second insulating layers having conductive vias formed therein interpose respective first and third insulating layers. The first and second conductive lines in the first insulating layer(s) are interconnected by the conductive vias to the first and second conductive lines, respectively, in the third layer(s) so as to interlace the first and second metal conductive lines together.

Abstract: The invention relates to a method for using checksums in X-tolerant test response compaction in scan-based testing of integrated circuits. Flip-flops of a chip are treated as points of a discrete geometrical structure described in terms of points and lines, with each point representing a MUXed flip-flop holding a value, each line representing a checksum, and each set of parallel lines representing scan chains. The checksums for the flip-flops are calculated along a direction.

Abstract: A routing pattern for high speed signals for a package substrate. Electrically conductive bond fingers are disposed on a first surface of the package substrate. The first surface is adapted to receive an integrated circuit in an attachment zone, and the bond fingers are disposed in at least two substantially concentric rings around the attachment zone. The bond fingers of the innermost ring of bond fingers are all routed to electrically conductive first traces disposed on a first layer of the package substrate. The bond fingers other that those on the innermost ring of bond fingers are all routed to electrically conductive second traces disposed on a separate second layer of the package substrate. The package substrate has electrically conductive traces on only the first layer and the second layer. Electrically conductive contacts are disposed on a substantially opposing second surface.

Abstract: A method for improving rate distortion performance of a compression system through parallel coefficient cancellation in a transform comprising the steps of (A) determining a block sum of absolute values for each of a plurality of blocks in a macroblock and (B) setting one or more coefficient values of a block to zero in response to a block sum value of said block being less than a first predetermined threshold value.

Abstract: An apparatus comprising a phase lock loop circuit and a control circuit. The phase lock loop circuit configured to generate an output signal having a first frequency in response to (i) an input signal having a second frequency, (ii) a first divider value and (iii) a second divider value. The second divider value may control spread spectrum modulation of the phase lock loop circuit. The control circuit configured to generate the second divider value in response to (i) the output signal and (ii) a programmable control signal.

Abstract: The present invention provides an architecture of a memory Built-In Self Repair (BISR) controller for connecting to N memory instances, where N is a positive integer greater than 1. The architecture includes N groups of data ports, N BISR_SUBMOD modules for connecting to the N memory instances, and a CLK_IN input port and a BISR_IN input port for setting configuration of the memory BISR controller. Each of the N groups of data ports includes (1) a PHY_IN output port for connecting to input of a corresponding memory instance; (2) a PHY_OUT input port for connecting to output of the corresponding memory instance; (3) a LOG_IN input port for sending signals to the corresponding memory instance; and (4) a LOG_OUT output port for receiving signals from the corresponding memory instance. Each of the N BISR_SUBMOD modules includes a flip-flop, a first mux and a second mux. The CLK_IN input port is connected to clock inputs of all N flip-flops of the memory BISR controller.

Abstract: An apparatus generally having a first circuit and a second circuit for motion estimation is disclosed. The first circuit may be configured to (i) generate a first motion vector for a block at an integer-pel resolution and (ii) determine a single block size associated with the first motion vector. The second circuit may be configured to (i) generate a plurality of second motion vectors at a sub-pel resolution by searching proximate the first motion vector using the single block size and (ii) determine a motion vector for the block as a particular one of the second motion vectors best matching a plurality of reference samples.

Abstract: A method and system for synchronizing recording of data transferred from a video source device to a recording device is disclosed. The method and system include analyzing an input signal from the source device based on a set of rules. In response to detecting a source device state change, the behavior of the recording device is automatically synchronized to the detected source device state without real-time user-interactive control. More particularly, when normal play mode is detected, the recording device automatically begins recording the input signal without user control or an extra control channel.

Abstract: A method and system for performing diagnostics and validation operations on a device under test uses near natural language commands. A host machine controls the testing either locally or remotely, such as through the Internet. Various options for running a test or battery of tests on the device under test include entering commands through a prompt line on a graphical user interface, reading commands from a file, or manipulating graphical objects representing components or devices and operations on a graphical user interface. A script may serve as a metric to determine the successfulness of a test or battery of tests of the device under test.

Abstract: A method for verifying reticle enhancement technique latent image sensitivity to mask manufacturing errors. The method includes the steps of revising a polygon based on mask CD distributions to provide a virtual mask, imaging the virtual mask to obtain response function statistical parameters, and comparing the statistical parameters to process tolerance requirements. Preferably, the method includes the steps of simulating an aerial and/or latent image of the virtual mask, calculating response functions based on the mask image simulation, collecting measurements and calculating statistical parameters based on the response functions, and comparing the statistical parameters with design rule requirements (i.e., for DI yield percentage for required mask manufacturing specification). The virtual mask is obtained by using mask CD distribution to induce statistical variations to layouts which have passed through the conventional OPC procedure.

Abstract: A method of routing an integrated circuit package includes receiving as input a placement and routing of at least a portion of an integrated circuit package design, selecting a set of at least three trace segments from the placement and routing that includes at least one inner trace segment routed between two outer trace segments, calculating an inner line function for the inner trace segment that is equally spaced from one of an adjacent line function, an adjacent outer line function, and an adjacent outer trace segment on each side of the inner line function, calculating a pair of end points for the inner line function, and generating as output a new routing that reroutes the inner trace segment collinearly with the inner line function and terminates the inner trace segment by the pair of end points.

Abstract: Techniques for vaporizing and handling a vaporized metallic element or metallic element salt with a heated inert carrier gas for further processing. The vaporized metallic element or salt is carried by an inert carrier gas heated to the same temperature as the vaporizing temperature to a heated processing chamber. The metal or salt vapor may be ionized (and implanted) or deposited on substrates. Apparatus for accomplishing these techniques, which include carrier gas heating chambers and heated processing chambers are also provided.

Abstract: A hardware-controlled data protection scheme can be used on a device providing buffering between two different protocols, especially where at least one of the protocols does not use fixed length blocks. A fixed block size is arbitrarily imposed on the data in order to calculate a cyclical redundancy code (CRC) for the block. Block sizes are restricted to a value of 2n, e.g., 2, 4, 8, 16, etc. The device is able to time-share and to receive or send data on more than one port while sharing the CRC engine between the ports. Intermediate values of the CRC for a given port are temporarily saved in a CRC register file. As a block of data for a given port is completed, a final CRC value for the block is saved to a CRC random access memory (RAM) located on the device and the entry in the register file is cleared. When the data is then output from the device, the CRC for the block is recalculated and checked against the saved value to be sure that they match.

Abstract: Apparatus and methods for an improved priority encoder using only static circuit components. Features and aspects hereof rely exclusively on static logic circuits exclusive ROM and other memory structures as relied on in prior structures. The exemplary static circuit structures relied upon in accordance with features and aspects hereof are less susceptible to leakage current and other issues common in high density integrated circuit applications. Thus, features and aspects hereof avoid use of ROM and other similar memory devices in favor of digital encoders comprised of static logic circuits cascaded through multiplexers to provide priority encoding in digital circuit applications coupling multiple devices to a shared, common bus structure.

Abstract: A semiconductor chip is provided which includes active and inactive IP cores. The spaces on the metal layer associated with the inactive IP cores includes voltage contrast inspection structures. The voltage contrast inspection structures serve to provide improved planarization of the metal layer and provided improved inspection capabilities.

Abstract: A method for implementing non-reference frame prediction in video compression comprising the steps of (A) setting a prediction flag (i) “off” if non-reference frames are used for block prediction and (ii) “on” if non-reference frames are not used for block prediction, (B) if the prediction flag is off, generating an output video signal in response to an input video signal by performing an inverse quantization step and an inverse transform step in accordance with a predefined coding specification and (C) if the prediction flag is on, bypassing the inverse quantization step and the inverse transform step.

Abstract: A method for developing a circuit design is disclosed. The method generally include the steps of (A) generating a violation display based on violation information provided from a place-and-route tool and (B) generating a layout display based on layout information provided from the place-and-route tool. The violation display may include (i) a plurality of performance violations for the circuit design and (ii) a plurality of user inputs each associated with one of the performance violations. The layout display may include a layout view of the circuit design. The layout view may highlight at least one of (i) a plurality of cells and (ii) a plurality of networks each along a path related to a particular one of the performance violations identified by a user through the user inputs.

Abstract: An on-chip substrate voltage controller which includes a plurality of chains of interconnected loaded ring oscillators connected to a multiplexer, where the multiplexer is configured to average the outputs from all the chains of interconnected loaded ring oscillators. An output of the multiplexer is connected to a comparator, such as a phase detector. The comparator also receives an output from a PLL, and is configured to compare the output of the multiplexer to the output of the PLL. An output of the comparator is connected to the controllable voltage regulator. The controllable voltage regulator receives a voltage in as well as the output of the comparator, and applies a substrate bias depending on what is received from the comparator.

Abstract: The present invention pertains to a system and method for specifying links, connectivity and bandwidth in an interconnect fabric. For example, a method for allocating connectivity and bandwidth of an integrated circuit may include receiving an interconnect fabric description, the described interconnect fabric having a plurality of platforms linked over an isochronous interconnect fabric. An arrangement of links of the received interconnect fabric is virtualized based on bandwidth. An arrangement of links of the received interconnect fabric is virtualized based on connectivity. The links are allocated on the basis of the virtualized link arrangements based on bandwidth and connectivity.

Abstract: A system for layout of a module in an integrated circuit layout pattern has a cell library and a cell placement system. The cell library includes a plurality of cells. The cell placement system is adapted to select one or more cells from the cell library and to locally place each selected cell within the module layout so that each cell pin of the selected cells and each port of the module layout occupies a unique vertical routing track within the module layout.