Abstract: A family of package substrates adapted to receive a family of integrated circuits having different sizes and provide electrical connections between the integrated circuits and a circuit board. Each package substrate in the family includes a package substrate having a die side and a circuit board side. The package substrate has a size that is consistent for all of the package substrates in the family of package substrates. The die side has integrated circuit contacts disposed in a pattern designed to make electrical connections to a given integrated circuit in the family of integrated circuits for which the package substrate is designed, as defined by locations of contacts on the given integrated circuit. The circuit board side has circuit board contacts disposed in a pattern and with functional assignments that are consistent for all of the package substrates in the family of package substrates.

Abstract: A data collection system. A data input form receives data, and a message queue receives the data from the data input form, and temporarily manages the data until the data collection system can process the data. A temporary data storage temporarily stores the data received by the message queue while waiting for the data collection system to process the data. A transaction manager receives the data from the message queue and processes the data. A data logger logs the processing transactions of the transaction manager. A data loader receives the data from the transaction manager and prepares the data for storage. A data storage device receives the data from the data loader.

Abstract: A method for tracing paths within a circuit includes receiving a transistor level netlist description. After receiving the transistor level netlist, convert the transistor level netlist to a transistor level data structure. Then, convert the transistor level data structure to a set of channel connect groups (CCG). A directed graph of the CCG may be generated.

Abstract: Provided are systems and methods for overcoming optical errors occurring from reticle and other hardware usage in a semiconductor fabrication apparatus. The systems and methods minimize optical errors, such as those resulting from gravitational sag on a reticle or mask, for a pattern being projected onto a wafer. The reduced errors allow larger reticles and masks to be used—while maintaining optical accuracy; and also improve optical budget management.

Abstract: A method for determining a timing margin to be applied in an integrated circuit timing design. Circuit simulator path delays and static timing analysis tool path delays are determined for the integrated circuit timing design. The circuit simulator path delays are plotted in a first plot versus a percentage difference between the circuit simulator path delays and the static timing analysis tool path delays, and in a second plot are plotted versus a numerical difference between the circuit simulator path delays and the static timing analysis tool path delays. A first point is identified on the second plot having a largest numerical difference, and the circuit simulator path delay for the first point is identified. A corresponding point on the first plot having the circuit simulator path delay is found, and the percentage difference for the corresponding point is identified. A combination of both the circuit simulator path delay and the percentage difference is used as the timing margin.

Abstract: A method for prototyping an integrated circuit may include selecting at least one daughter card for connection to a motherboard. The daughter card is selected having an ability to provide functionality corresponding to a specific integrated circuit device. The at least one daughter card is connected to the motherboard so that the daughter card is communicatively connected to common memory provided on the motherboard. The at least one daughter card and motherboard emulate an integrated circuit design. At least one of software and system integration of the integrated circuit emulated by the motherboard and the at least one daughter card is tested.

Abstract: Disclosed is a system using a SAS host controller and SAS expanders to control multiple SATA end devices where the memory contained on the SAS host controller is fixed to ease the cost and power consumption of the SAS host controller device, but where there is an expanded ability to support additional SATA end devices by configuring the allowed native command queue depth to be smaller for each SATA end device, thus allowing more SATA end devices to be supported by a single SAS host controller. An embodiment of the invention has three possible preset configuration states: thirty-two SATA end devices with a native command queue depth of thirty-two; sixty-four SATA end devices with a native command queue depth of sixteen; and one-hundred-twenty-eight SATA end devices with a native command queue depth of eight.

Abstract: A method for interconnecting sub-functions of metal-mask programmable functions that includes the steps of (A) forming a base layer of a platform application specific integrated circuit (ASIC) comprising a plurality of pre-diffused regions disposed around a periphery of the platform ASIC, (B) forming two or more sub-functions of a function with a metal mask set placed over a number of the plurality of pre-diffused regions of the platform application specific integrated circuit and (C) configuring one or more connection points in each of the two or more sub-functions such that interconnections between the two or more sub-functions are tool routable in a single layer. Each of the pre-diffused regions is configured to be metal-programmable.

Abstract: The present invention is directed to a system and method for improving transition delay fault coverage through use of augmented flip-flops (TL flops) for a broadside test approach. The TL flops use the same clock for scan and functional operation. Thus, the TL flops do not require a fast signal switching between launch and test response capture. Each of the TL flops includes additional multiplexer in front of a standard scan flop and a transition enable (TEN) signal. Moreover, only a heuristically selected subset of scan flip-flops is replaced with the TL flops and only one additional MUX per selected scan flip-flop may contribute an area overhead. Consequently, the overall chip area overhead may be minimal. The present invention may be suitable for being implemented with currently available third party ATPG.

Abstract: Data cells of plural classes are transferred from input ports to output ports through a switch by storing the cells at each input port in class-specific virtual output queues (VOQ) within sets of VOQs associated with output ports, and providing credits to VOQs according to class-associated guaranteed bandwidths. When a cell is received at a VOQ having credits, a high-priority request for transfer is generated. If a cell is received at a VOQ that does not have any available credits, a low-priority request for transfer is generated. In response to requests, grants are issued to VOQ sets without regard to class, high-priority requests being favored over low-priority requests. When a grant is received for a particular VOQ set, an arbitrator selects a VOQ from the set, giving priority to VOQs having credits over VOQs without credits, and a cell from the selected VOQ is transferred.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a plurality of match signals in response to an incoming data signal. Each match signal is generated in response to different search criteria. The second circuit may be configured to present a protocol indication signal in response to the plurality of match signals.

Abstract: A switching fabric connects input ports to output ports. Each input has an input pointer referencing an output port, and each output has an output pointer referencing an input port. An arbiter includes input and output credit allocators, and an arbitration module (matcher). The input credit allocator resets input credits associated with input/output pairs and updates the input pointers. Similarly, the output credit allocator resets output credits associated with input/output pairs and updates the output pointers. The matcher matches inputs to outputs based on pending requests and available input and output credits. A scheduler schedules transmissions through the cross-bar switch according to the arbiter's matches.

Abstract: A therapeutic instrument for the ergonomic, effective and safe opening and closing of targeted remote tissue sites; includes a pistol grip style handle with a hand activated lever for needle deployment and, optionally, with features to control tissue cutting and guide wire installation; also incorporates a specialized elongated rigid or flexible instrument shaft, which enables vacuum assisted holding of tissue at a uniquely contoured distal tip, where placement of a suture in a purse string configures occurs along with, if desired, tissue cutting and guide wire passage.

Abstract: A method for characterizing the current as a function of applied electric field for a resistor exposed to a high electric fields is described. The method uses current versus voltage measurements at low electric fields, where the resistor is not damaged and the current does not saturate. An example illustrating the importance of such resistor characterization is provided.

Abstract: A tool for facilitating automatic test pin assignment for a programmable platform device including a process for collecting information related to the programmable platform device, a process for automatically initializing a test pin assignment for the programmable platform device, a process configured to receive user specifications for IOs and a process for performing dynamic test pin reassignment in response to the user specifications.

Abstract: Methods and systems assess timing of PCI signals. A test mode is initiated within a host adapter board. A clock signal is generated for the host adapter board. PCI signals are generated within the host adapter board. One or more PCI signal lines of the host adapter board are electronically selected; and timing (e.g., slew rate and/or clock-to-signal valid) of the one or more PCI signal lines is assessed.

Abstract: A method and tool that capture, create, and integrate a clock specification to achieve a correct-by-construction design flow of a semiconductor product from a partially manufactured semiconductor platform. The clocking elements of the design flow are combined and displayed in a plurality of context-driven views. Within each view, details of the clock specification are presented in the context of the information. A user may zoom in/out through the plurality of views of the design flow for more or less detailed information. Each view can combine the logical, structural, architectural, cost, timing, and other features of the clock in a particular context. A user can zoom in to select and manipulate circuit elements. The user can then zoom out and the present invention determines how changes affect other clocks in the same or other modules and/or the same clock in other modules.

Abstract: The present invention is a method for coercing disk drive capacity in a RAID configuration. The method includes the step of determining actual disk drive capacities of a first disk drive and a second disk drive in the RAID configuration. If the actual disk drive capacities of the first disk drive and the second disk drive differ, the method further includes multiplying the smaller actual disk drive capacity by a coercion ratio to establish an optimal disk drive capacity. The optimal disk drive capacity sets a minimum capacity threshold for any disk drive utilized within the RAID configuration. If the actual disk drive capacities of the first disk drive and the second disk drive are an equal value, the method further includes multiplying the value by the coercion ratio to establish the optimal disk drive capacity.

Abstract: Methods and associated structure for utilizing multiple ports or PHYs comprising a SAS wide port to improve transmission bandwidth utilization for a single large I/O request. In one aspect hereof, a large I/O request is broken into a plurality of smaller I/O requests to be distributed over multiple PHYs or ports of a configured wide SAS port. The number of smaller I/O requests may be any number up to the maximum number of PHYs or ports comprising the SAS wide port. In another aspect hereof, the size of a large I/O request may be compared against a threshold value to determine whether the large request should be broken into smaller requests. The threshold value may be determined in accordance with features and aspects hereof either statically or dynamically based on workloads assigned to, and utilization of, the configured SAS wide port.

Abstract: Color-difference signals that become unnecessary after rotation are deleted from a second pixel while saving color-difference signals that become necessary after rotation in the second pixel, to thereby form image data conforming to YUV422 format. The image data is then rotated, and subsequently the color-difference signals saved in the second pixel are returned to the original first pixel, to thereby form image data conforming to YUV422 format.