Abstract: A deep n-well is formed beneath the area of an inductor coil. The use of a deep n-well lessens the parasitic capacitance by placing a diode in series with the interlayer dielectric cap. The deep n-well also reduces substrate noise. Once the n-well is implanted and annealed, a cross hatch of shallow trench isolation is patterned over the n-well. The shallow trench isolation reduces and confines the inductively coupled surface currents to small areas that are then isolated from the rest of the chip.

Abstract: The present invention is directed to a method and apparatus for exposing pre-diffused IP blocks in a semiconductor device for prototyping based on hardware emulation. Addresses may be provided to multiplexers through configuration pins. The input ports of the multiplexers may be connected to interface pins of the pre-diffused IP blocks, and the output ports of the multiplexers may be connected to I/O pins which provide input and output to the semiconductor device. Through controlling the signals on the configuration pins and thus the outputs of multiplexers, any single pre-diffused IP blocks or any combination of the pre-diffused IP blocks in the semiconductor device may be exposed through corresponding I/O pins for prototyping.

Abstract: Embodiments of the invention include a method for electro chemical mechanical polishing of a substrate. The process includes flowing an electro chemical mechanical polishing (ECMP) slurry having a high viscosity with a polishing agent over a portion of the substrate. Electrical current is passed through the slurry and substrate. The electrical current, in conjunction with the abrading action of the slurry as it flows over the surface of the substrate, serves to remove at least a portion of the metal layer from the substrate. The invention also includes various slurry embodiments.

Abstract: An improved Content Addressable Memory (CAM) architecture and method for operating the same is provided herein. The improved CAM architecture may generally include an array of memory cells arranged into rows and columns, where each row includes a number of memory cells configured for storing one word. In particular, the number of memory cells may be coupled to a plurality of local match lines which, when combined through a hierarchy of two or more logic gates, form a match line signal for the entire word. Dynamic logic is used within a compare portion of each memory cell to reduce the occurrence of functional failures. In addition, the improved method for operating the CAM reduces power consumption and peak current, and improves timing, by eliminating the need to restore the match line voltage to a preset voltage level before each new compare operation.

Abstract: A refresh controller transmits two refresh request signals of a first request signal which indicates a time at which a refresh operation of a DRAM may be performed and a second request signal which indicates a time at which a refresh operation of the DRAM must be performed, to an arbitrator. On the other hand, also transfer request signals each of which requests a data transfer are transmitted from plural data transfer parts, respectively, to the arbitrator. If no transfer request signal is input when a first request signal is input to the arbitrator, a refresh operation of the DRAM is performed. As a result, a refresh operation is performed when the crowding level of a bus is relatively low. This improves an efficiency in a data transfer.

Abstract: A system and method for collecting and analyzing optical inspection results obtained during the manufacturing process and comparing those results to actual functional results of a specially designed test vehicle integrated circuit. The test vehicle integrated circuit allows failures to be localized to very small areas, which allows more accurate correlation between inspection faults and functional failures. The correlation of inspection faults to actual functional failures is used to change the sensitivity settings for an optical inspection system to more accurately detect defects that are likely to be functional failures.

Abstract: Disclosed is a netlist query language that reads and updates electrical circuit data stored in a netlist database that stores electrical circuit data parsed from a netlist text file. To obtain the netlist text file, an electrical circuit schematic of an electrical circuit is created using a commercially available electrical schematic capture software tool. The electrical schematic capture software tool is then directed to create the netlist text file that is representative of the electrical circuit. The netlist text file is then parsed, and the parsed netlist data that is representative of the electrical circuit is stored in the netlist database. The netlist database provides netlist database access subroutines that allow a software program to read and update data stored in the netlist database. Sophisticated programming skills are required to read and update the netlist database using the netlist database access subroutines.

Abstract: Embodiments of the invention include a controller apparatus, system and method for transferring data between data storage devices within a computer system. The inventive controller apparatus includes device interface logic for connecting the controller to a plurality of data storage devices, e.g., a hard disk device and a CD-RW device, and host interface logic for connecting the controller to a host or host computer via a bus such as a PCI bus. The host includes a number of other components, e.g., a host memory, connected thereto. The controller includes switching circuitry that allows data to be transferred directly from the source data storage device to at least one destination data storage device, i.e., without the transferred data passing from the controller through the bus to the host and/or the host memory.

Abstract: A library useable to facilitate testing of IO cells of an ASIC. The library includes IO cell identifications and test structures associated with the IO cell identifications, and identifies which test structures are required to test which IO cells. Preferably, the library forms part of an ASIC design system. A method of testing IO cells of an ASIC is also provided, and includes using the library to determine which test structures to use to test the IO cells, and testing the IO cells using the test structures.

Abstract: The present invention provides a RRAM communication system including at least one RRAM controller and a master controller. The master controller is communicatively coupled to each of at least one RRAM controller. The master controller is suitable for loading test input parameters into at least one RRAM controller, starting execution of a test and obtaining a result of test execution from at least one RRAM controller. Each of at least one RRAM controller is suitable for executing different tests depending on commands received from the master controller.

Abstract: Embodiments of the invention include an integrated circuit including a line driver. The integrated circuit includes a voltage mode driver comprising complementary first and second input voltage drivers, a programmable resistor network and a current mode driver. The programmable resistor network allows the amplitude of the line driver outputs to be controlled based on the particular resistor connections in the programmable resistor network. Also, the differential impedance of the integrated circuit and the common mode impedance of the integrated circuit are based on the resistance values of the resistors in the programmable resistor network.

Abstract: A method and apparatus for calculating ramptime propagation for integrated circuit layout patterns having pins interconnected in an oriented graph in one or more closed loops is described. Ramptime values are calculated for a first set of the pins, which are not connected to a closed loop while leaving a second set of the pins with unknown ramptime values. One or more closed loops are identified by backtracking from the pins in the second set with unknown ramptime values. A ramptime value for each pin in the one or more closed loops is calculated iteratively.

Abstract: A Gaussian noise is simulated by discrete analogue ri,j. A first parameter ? and pluralities of first and second integers i and j are selected. A plurality of points i,j are identified and a magnitude si,j is calculated for each point based on ?, i and j. The discrete analogue ri,j is based on a respective si,j. Examples are given of ? = 2 B - A 2 B and D>i?0 and 2C>j?0, where B?0, 2B>A>0, C?1 and D?1, and magnitude s i , j = 1 - ? i + ? i · 1 - ? 2 C · j ? ? ? or ? ? ? s D - 1 , j = 1 - ? D - 1 + ? D - 1 · 1 2 C · j . In some embodiments, a segment is defined based on ? and i. The segment is divided into points based on respective values of j, and the magnitude is calculated for each point of the segment. The defining and dividing segments and calculating the magnitude is iteratively repeated for each value of i.

Abstract: Embodiments of the invention include a copper interconnect structure having increased electromigration lifetime. Such structures can include a semiconductor substrate having a copper layer formed thereon. A dielectric barrier stack is formed on the copper layer. The dielectric barrier stack includes a first portion formed adjacent to the copper layer and a second portion formed on the first portion, the first portion having improved adhesion to copper relative to the second portion and both portions are formed having resistance to copper diffusion. The invention also includes several embodiments for constructing such structures. Adhesion of the dielectric barrier stack to copper can be increased by plasma treating or ion implanting selected portions of the dielectric barrier stack with adhesion enhancing materials to increase the concentration of such materials in the stack.

Abstract: A method for selecting test site locations on a substrate, by a) specifying a subset of all test site locations on the substrate, and b) selecting a desired number of candidate test site locations from within the subset of test site locations on the substrate. c) While selecting one of the candidate test site locations and holding all others of the candidate test site locations as fixed, determining a new location for the selected one of the candidate test site locations, which new location increases a test sensitivity, as estimated by a trace of a variance-covariance matrix. d) Repeating step (c) for each candidate test site location in the subset of test site locations, to produce a finalized set of candidate test site locations, until a desired end point is attained.

Abstract: In an OTP memory, initially, a file A is recorded. When modification of the file A is needed, a modification file B is additionally written into the OTP memory. Storage information on the modification file B is also additionally written into a FAT area and a directory entry. When an application program issues a read request for the file A, a file system refers to the FAT area and the directory entry to recognize the existence of the modification file B and reads the file A and the modification file B out from a data area. Then, the file system modifies the file A on the basis of the modification file B and stores a modified file into a RAM. The application program accesses the file which is stored in the RAM.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an output signal oscillating at a first frequency in response to (i) a first control signal, and (ii) a second control signal. The second circuit may be configured to generate the second control signal in response to (i) an input signal having a voltage and (ii) the output signal. The second circuit may be configured to compare a peak voltage of the output signal to the input voltage.

Abstract: Disclosed is a 2-level cache system for a Redundant Array of Independent Disks (RAID) device used as part of a Storage Area Network (SAN) system. The RAID controller of the RAID device contains a level 1 cache contained in the RAID controller RAM, and a level 2 cache is created in a Log-structured File System (LFS) portion of a local hard disk drive of the RAID device. The 2-level cache system provides increased data integrity and reliability, as well as less fragmentation of the data frame, for communications with remote storage devices in a SAN system. The increased performance is due to data caching being done at the RAM and disk level instead of data being sent directly to the transmit buffer. The 2-level cache system delays data transmissions until there is system idle time, thus, providing efficient bandwidth utilization of SAN communications, as well as improved resource allocation at the RAID controller level.

Abstract: A test circuitry approach which addresses the shortcoming associated with current process monitor circuitry. The approach provides a means of testing that can be employed in association with any and all tester platforms. On-chip built-in self test (BIST) circuitry is added to the design that analyzes the 10-bit value captured from the counter, and indicates to the ATE via a single pin at a single test vector location whether or not the device has passed its test limits. An alternative solution is to use the digital capture circuitry on a mixed-signal tester to capture the non-deterministic digital word generated by the process monitor circuitry, and then test that result against the desired test limits.

Abstract: The present invention provides an optimized direct write lithography system using optical mirrors. That is, a maskless lithography system is provided. The maskless direct-write lithography system provided uses an array of mirrors configured to operate in a tilting mode, a piston-displacement mode, or both in combination. The controlled mirror array is used as a substitute for the traditional chrome on glass masks. In order to avoid constraining the system to forming edges of patterns aligned with the array of mirrors, gray-scale techniques are used for subpixel feature placement. The direct-writing of a pattern portion may rely on a single mirror mode or a combination of modes.