Abstract: A computerized engineering database feedback system provides special processing instructions for processing materials in a production process, and provides historical information related to the materials processed according to the special processing instructions. The system includes a request entry device through which requesting personnel may input special processing information indicating a way to process the materials differently from a normal way of processing of the materials. An instruction processing device receives the special processing information and generates the special-processing instructions based thereon. A process station device receives the special-processing instructions, and presents the special-processing instructions to material-processing personnel.

Abstract: A simulation test bench environment for testing a circuit is described. The test bench environment uses high-level task routines executed by one or more bus functional device models to generate input test vectors. A timing and protocol checker verifies both signal timing and functional operation bus specifications. Data and parity miscompares and corruptions are reported in real-time during simulation. An error and interrupt handler services errors and interrupts by communicating with the buses coupled to the circuit to execute specific recovery routines. A memory model is used to generate known expected data for data transactions, to store data from the circuit on data transactions, and to generate operation codes for the circuit.

Abstract: A variable-gain amplifier circuit includes an input port, an output port, and first and second amplifiers coupled therebetween. The first amplifier includes a first amplifier path having a first amplification factor, effective when the input signal has a voltage level in a first range, and a second amplifier path having a second amplification factor greater than the first amplification factor, effective when the input signal has a voltage level in a second range including voltages of a first polarity greater than that in the first range. The second amplifier includes a third amplifier path having the first amplification factor, effective when the input signal has a voltage level in a third range, and a fourth amplifier path having the second amplification factor, effective when the input signal has a voltage level in a fourth range including voltages of a second polarity greater than that in the third range.

Abstract: The present invention provides a luminaire component housing which has at least two upwardly opening pockets substantially equal to the heights of the components to be fitted therein. The component housing has a cover which cinches the components into their respective pockets, thereby eliminating the need for metal straps, screws or other traditional hardware to secure components into place.

Abstract: A CAM testing procedure detects storage logic faults, comparison logic faults, and faults caused by interactions between the storage and comparison logic for both single port and dual port CAM's. To uncover faults in the storage logic, a series of read and write operations are performed, either using a standard test sequence, such as the March C algorithm, or any other desired test sequence. The CAM test, however, intermixes comparison operations with the read and write operations to uncover faults in the comparison logic. For dual port memories, the test sequence comprises executing comparison operations concurrently with the read and/or write operations, thus revealing faults between the storage and comparison logic. For single port memories, the test sequence comprises performing a comparison operation following the read/write operations at each address, immediately verifying the comparison logic at each address.

Abstract: A method of generating a cell function and timing model library in a standard library format includes the steps of (a) receiving as input a model source file, a technology dependent file, and a cell list data file; (b) parsing a functional description for each cell in the cell list data file from the model source file; (c) expanding parameterized timing data for each cell in the cell list data file from the technology dependent file; and (d) generating as output a cell model library in a standard library format from the parameterized timing data.

Abstract: The present invention is directed to an apparatus suitable for mounting an integrated circuit (IC) including a frame suitable for receiving an integrated circuit (IC). The frame includes at least one leg coupled to the frame, the leg suitable for engaging a circuit board so as to enable the apparatus to be secured to the circuit board, thereby securing the integrated circuit (IC). At least one of the frame and leg include a conductive material so as to create at least one of a heat conducting path and an EMC ground path between the integrated circuit (IC) and the circuit board.

Abstract: A system, such as an AMBA based system, wherein an interrupt controller is coupled directly to a processor, thereby providing that the processor can access the interrupt controller without having to access a system bus. Specifically, the interrupt controller may be coupled to a port of the processor, such as a tightly coupled memory (TCM) port or a coprocessor port of the processor. The interrupt controller may be coupled to the TCM port along with SRAM.

Abstract: An improvement to a process for manufacturing complementary metal oxide semiconductor devices on a monolithic substrate, where the improved process forms nonvolatile memory devices and programmable logic devices. The improvement includes exposing gate electrodes of a selected portion of the complementary metal oxide semiconductor devices at a point in the process where the gate electrodes have been previously covered by a protective material layer. A capacitive material layer is deposited on the monolithic substrate, such that it contacts the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices. A top electrode material layer is deposited on the monolithic substrate, such that the top electrode material layer contacts the capacitive material layer in a region overlying the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices.

Abstract: A process for forming a capacitive structure and a fuse structure in an integrated circuit device includes forming a first capacitor plate and first and second fuse electrodes in a first dielectric layer of the device. In a second dielectric layer overlying the first dielectric layer, a capacitor dielectric section overlying the first capacitor plate, and a fuse barrier section overlying and between the first and second fuse electrodes are formed simultaneously. In a conductive layer overlying the second dielectric layer, a second capacitor plate overlying the capacitor dielectric section, and a fuse overlying the fuse barrier section and contacting the first and second fuse electrodes are formed simultaneously. The capacitor dielectric section and the fuse barrier section may be defined simultaneously by selectively removing portions of the first dielectric layer during a single etching step.

Abstract: The present invention provides a transmission equalization system for use with an integrated circuit package employing a substrate. In one embodiment, the transmission equalization system includes a signal transmission subsystem having a pair of transmission line conductors located in the substrate and employing a differential electrical signal. The transmission equalization system also includes an equalization subsystem located proximate the pair of transmission line conductors that employs at least one aperture positioned and oriented to provide a substantially equivalent transmission environment for each of the pair of transmission line conductors.

Abstract: A circuit and method for generating a write enable pulse that is independent of the clock duty cycle and the clock frequency. The circuit includes a pulse generator for generating a pulse in response to a clock signal and a write enable signal generator for generating a write enable pulse. The pulse tracks the leading edge of the clock signal. A logic circuit is coupled to the pulse generator and the write enable signal generator to generate the write enable pulse by combining the pulse and the write enable signal.

Abstract: A method of datapath cell placement is disclosed that minimizes signal propagation time through a datapath macro and datapath macro area that includes the steps of receiving a datapath description of constrained input pins, unconstrained input pins, and output pins for a datapath block; assigning a first corresponding first cell level to a first datapath cell in a data path of a constrained input pin wherein the first corresponding first cell level is representative of a number of intervening datapath cells between the first datapath cell and the constrained input pin; assigning a second corresponding first cell level to a second datapath cell in a data path connecting the first datapath cell to an unconstrained input pin that is substantially identical to the first corresponding first cell level; and assigning a corresponding second cell level to the datapath cell in the data path connecting the first datapath cell to the unconstrained input pin wherein the second cell level is representative of a number of

Abstract: A positive photoresist bead is removed from an edge surface of a substrate by exposing the photoresist bead with light from an exposing source along a plurality of non-parallel paths approximately normal to the surface of the photoresist bead. The light may be simultaneously directed by a light guide along the non-parallel paths, or a mount may support the light guide adjacent the bead to move the light guide to various positions to direct the light along the non-parallel paths. Alternatively, plural light sources direct light to the bead along non-parallel paths. In any case, the exposed photoresist bead is then removed with a solvent.

Abstract: Disclosed is a process of electrically coupling the gate electrodes of an N-type transistor and a P-type transistor without causing substantial cross diffusion of P-type dopants into the N-type gate electrode and N-type dopants into the P-type gate electrode. This is possible because some or all annealing and diffusion steps are performed while the N-type and P-type gate electrodes are physically isolated from one another. Also disclosed is a Silicide as Diffusion Source process in which dopant atoms implanted in silicide regions diffuses out of the silicide regions and into the substrate to form source and drain diffusions. During this diffusion step adjacent N-type and P-type gate electrodes remain unconnected to prevent cross diffusion. Then, these two electrodes are electrically connected by a local interconnect. The local interconnection is a conductive path formed at about the level of the polysilicon (i.e.

Abstract: An improvement to a process for manufacturing complementary metal oxide semiconductor devices on a monolithic substrate, where the improved process forms nonvolatile memory devices and programmable logic devices. The improvement includes exposing gate electrodes of a selected portion of the complementary metal oxide semiconductor devices at a point in the process where the gate electrodes have been previously covered by a protective material layer. A capacitive material layer is deposited on the monolithic substrate, such that it contacts the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices. A top electrode material layer is deposited on the monolithic substrate, such that the top electrode material layer contacts the capacitive material layer in a region overlying the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices.

Abstract: A phase measurement circuit includes first and second complementary clock strobe inputs, a local clock input and a sample clock output. A programmable delay line is coupled between the local clock input and the sample clock output and has a plurality of propagation delay settings. First and second toggle circuits are clocked by the first and second clock strobe inputs, respectively, and each has a toggle output that changes state when clocked by the respective first or second clock strobe input. A capture latch circuit has first and second data inputs coupled to the toggle outputs of the first and second toggle circuits, respectively, has first and second capture outputs, and is clocked by the sample clock output. A synchronizer circuit has first and second data inputs coupled to the first and second capture outputs, respectively, has first and second synchronized capture outputs, and is clocked by the local clock input.

Abstract: A single-chip integrated circuit includes a memory array, a built-in self test circuit and a pause circuit. The built-in self test circuit is coupled to the memory array and is adapted to execute a sequence of write and read operations on the memory array. The pause circuit is coupled to and activated by the built-in self test circuit. When activated, the pause circuit pauses the sequence of write and read operations for a pause time period.

Abstract: To reduce FIFO access cycles across a system bus in a multi-processor system in which two processors communicate across a system bus through a FIFO, two separate FIFO descriptors are provided. The first descriptor is maintained by the processor located on-board with the FIFO, and the second descriptor is maintained by an off-board processor which communicates with the FIFO across the bus. When one processor performs a FIFO operation, the processor updates the other processor's descriptor via a memory access across the bus. Additionally, one module passes credits to the other to indicate that the latter has permission to perform a plurality of FIFO operations consecutively. In one embodiment a special non-valid data value is used to indicate an empty FIFO position.

Abstract: A physical design automation system produces an optimal placement of microelectronic components or cells on an integrate circuit chip. An initial population of possible cell placements is generated, and repeatedly altered using simulated on or other fitness improvement algorithm to progressively increase the fitnesses (decrease the costs) of the placements. After each alteration step, the fitnesses of the placements are calculated, and less fit placements are discarded in favor of more fit placements. After a termination criterion is reached, the placement having the highest fitness is designated as the optimal placement. Two or more fitness improvement algorithms are available, and are optimally switched from one to the other in accordance with an optimization criterion to maximize convergence of the placements toward the optimal configuration.