Patents Assigned to LSI
  • Method for multiprocessor communication within a shared memory architecture
    Patent number: 7035908
    Abstract: An apparatus comprising a shared memory and a multiprocessor logic circuit. The shared memory may be configured to store data. The multiprocessor logic circuit may comprise a plurality of processors and a message circuit. The message circuit may be configured to pass messages between the processors.
    Type: Grant
    Filed: July 26, 2001
    Date of Patent: April 25, 2006
    Assignee: LSI Logic Corporation
    Inventors: Kalvin E. Williams, John S. Holcroft, Christopher J. Lane
  • Quality measurement of an aerial image
    Patent number: 7035446
    Abstract: A method of measuring the quality of a simulated aerial image includes receiving as input a mask pattern for a chip design, simulating an aerial image of the mask pattern, calculating an error area representative of a deviation between an ideal boundary of the chip design and a boundary of the simulated aerial image, calculating maximum and average end-of-line deviations between the ideal boundary of the chip design and the boundary of the simulated aerial image, and displaying a worst quality area in the simulated aerial image as a function of the error area and the maximum and average end-of-line deviations for visual inspection.
    Type: Grant
    Filed: May 22, 2002
    Date of Patent: April 25, 2006
    Assignee: LSI Logic Corporation
    Inventors: Marina M. Medvedeva, Jaroslav V. Kalinin, Stanislav V. Aleshin, Nadya Strelkova
  • Dual damascene interconnect structure with improved electro migration lifetimes
    Patent number: 7033929
    Abstract: A dual damascene interconnect structure is formed by patterning a first dielectric to form a metal line. A second dielectric is disposed on the first dielectric and patterned to form a via. The first metal line is patterned in a configuration relative to a via landing so that a cavity is formed when the via etch into the second dielectric is extended into the first dielectric. The cavity is filled with a conductive metal in an integral manner with the formation of the via to form a via projection for improved electrical contact between the via and the metal line.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: April 25, 2006
    Assignee: LSI Logic Corporation
    Inventors: Peter A. Burke, William K. Barth, Hongqiang Lu
  • Process and apparatus for placement of cells in an IC during floorplan creation
    Patent number: 7036102
    Abstract: Objects are placed in a rectangle and their coordinates of the objects and are adjusted to establish a substantially uniform density of objects in the rectangle. The evaluation of coordinates is performed by placing the wires between cells coordinates and adjusting the cell coordinates to connect the cells to the wires. The substantially uniform density is achieved by dividing the rectangle into first and second rectangles having equal free areas and into third and fourth rectangles having equal areas of objects. The coordinates of the objects are adjusted based on boundaries between the first and second rectangles and between the third and fourth rectangles.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: April 25, 2006
    Assignee: LSI Logic Corporation
    Inventors: Alexander E. Andreev, Andrey A. Nikitin, Igor A. Vikhliantsev
  • Method for fabricating planar semiconductor wafers
    Publication number: 20060084267
    Abstract: The present invention relates to a method of fabricating planar semiconductor wafers. The method comprises forming a dielectric layer on a semiconductor wafer surface, the semiconductor wafer surface having vias, trenches and planar regions. A barrier and seed metal layer is then formed on the dielectric layer. The wafer is next place in a plating bath that includes an accelerator, which tends to collect in the vias and trenches to accelerate the rate of plating in these areas relative to the planar regions of the wafer. After the gapfill point is reached, the plating is stopped by removing the plating bias on wafer. An equilibrium period is then introduced into the process, allowing higher concentrations of accelerator additives and other components of the bath)] above the via and trench regions to equilibrate in the plating bath. The bulk plating on the wafer is resumed after equilibration.
    Type: Application
    Filed: October 14, 2004
    Publication date: April 20, 2006
    Applicant: LSI Logic Corporation, A Delaware Corporation
    Inventors: Byung-Sung Kwak, Peter Burke, Sey-Shing Sun
  • Non-volatile semiconductor memory and driving method
    Patent number: 7031192
    Abstract: A data control unit is used to proved program, erase and verify signals to a non-volatile metal-oxide3-nitride-oxide-semiconductor (MONOS) memory. The data control unit comprises a plurality of sub-units that each contains a sense amplifier, two bi-directional flip-flop latches coupled in series and a program, erase and verify circuit. The two flip-flop latches each perform a task as a master latch or a slave latch depending on the memory operation. The program, erase and verify circuit in each sub-unit are connected together in a serial fashion such that multiple verification results are accumulated into one final result. Control signals are exchanged between a chip control unit and the data control unit to perform specified memory operations.
    Type: Grant
    Filed: November 7, 2003
    Date of Patent: April 18, 2006
    Assignee: Halo LSI, Inc.
    Inventors: Ki-Tae Park, Tomoko Ogura
  • Configurable hardware register stack for CPU architectures
    Patent number: 7032104
    Abstract: A circuit comprising a register stack and a control circuit. The register stack may be configured as (i) a plurality of segments addressable through a segment address signal and (ii) a plurality of registers within each of the plurality of segments. The plurality of registers are generally addressable through a register address signal. The control circuit may be configured to (i) store a plurality of register states, (ii) store a segment count signal, and (iii) present the segment address signal responsive to the plurality of register states, the segment count signal, and the register address signal.
    Type: Grant
    Filed: December 15, 2000
    Date of Patent: April 18, 2006
    Assignee: LSI Logic Corporation
    Inventor: Peter Korger
  • Method for loosely coupling metadata and data in a storage array
    Patent number: 7032125
    Abstract: The present invention is a method and system for associating metadata with user data in a storage array in a manner that provides independence between metadata management and a storage controller's cache block size. Metadata may be associated with user data according to multiple fashions in order to provide a desired performance benefit. In one example, the metadata may be associated according to a segment basis to maximize random I/O performance and may be associated according to a stripe basis to maximize sequential I/O performance.
    Type: Grant
    Filed: April 25, 2002
    Date of Patent: April 18, 2006
    Assignee: LSI Logic Corporation
    Inventors: Keith W. Holt, William P. Delaney
  • Luminaire having symmetrically opposed asymmetrical reflectors
    Patent number: 7029148
    Abstract: A luminaire comprising a housing, plurality of reflectors, lamps and electrically connected lamp sockets. The luminaire has at least two asymmetrical reflectors that are symmetrically opposed to each other and ideally has at least one symmetrical reflector located between the asymmetrical reflectors.
    Type: Grant
    Filed: July 10, 2003
    Date of Patent: April 18, 2006
    Assignee: LSI Industries Inc.
    Inventors: Barry White, Steve Proner
  • Planarization with reduced dishing
    Patent number: 7029591
    Abstract: A method of forming a planarized layer on a substrate, where the substrate is cleaned, and the layer is formed having a surface with high portions and low portions. A resistive mask is formed over the low portions of the layer, but not over the high portions of the layer. The surface of the layer is etched, where the high portions of the layer are exposed to the etch, but the low portions of the layer underlying the resistive mask are not exposed to the etch. The etch of the surface of the layer is continued until the high portions of the layer are at substantially the same level as the low portions of the layer, thereby providing an initial planarization of the surface of the layer. The resistive mask is removed from the surface of the layer, and all of the surface of the layer is planarized to provide a planarized layer.
    Type: Grant
    Filed: April 23, 2003
    Date of Patent: April 18, 2006
    Assignee: LSI Logic Corporation
    Inventors: Wilbur G. Catabay, Wei-Jen Hsia, Hao Cui
  • Integrated circuits, and design and manufacture thereof
    Patent number: 7032190
    Abstract: A representation of a macro for an integrated circuit layout. The representation may define sub-circuit cells of a module. The module may have a predefined functionality. The sub-circuit cells may include at least one reusable circuit cell. The reusable circuit cell may be configured such that when the predefined functionality of the module is not used, the reusable circuit cell is available for re-use.
    Type: Grant
    Filed: December 1, 2003
    Date of Patent: April 18, 2006
    Assignee: LSI Logic Corporation
    Inventors: Stefan Auracher, Claus Pribbernow, Andreas Hils
  • Memory interface with write buffer and encoder
    Publication number: 20060080589
    Abstract: A method and apparatus are provided for interfacing between a data source and a tightly-coupled memory. In the method and apparatus, a write data word and a write address are received from the data source and latched in a first clock cycle within a write buffer along a write data path, between the data source and the memory. The write data word is encoded according to an error detection code along the write data path. The write address and the write data word are applied to the memory from the write buffer. The write data word is accessible to the data source from the write data path or the memory beginning with a second clock cycle, which is a next subsequent clock cycle to the first clock cycle.
    Type: Application
    Filed: October 7, 2004
    Publication date: April 13, 2006
    Applicant: LSI Logic Corporation
    Inventors: Jeffrey Holm, David Parker, Bradley Winter
  • Reliability circuit for applying an AC stress signal or DC measurement to a transistor device
    Publication number: 20060076972
    Abstract: An integrated circuit is provided, which includes a transistor device under test, an AC drive circuit, an AC bias circuit and a DC bias circuit. The AC drive circuit generates an AC drive signal. The AC bias circuit biases the transistor device under AC bias conditions in response to the AC drive signal. The DC bias circuit biases the transistor device under DC bias conditions. A switch circuit selectively couples the transistor device to the AC bias circuit in an AC stress mode and to the DC bias circuit in a DC measurement mode.
    Type: Application
    Filed: October 11, 2004
    Publication date: April 13, 2006
    Applicant: LSI Logic Corporation
    Inventors: John Walker, SangJune Park, Richard Schultz
  • Method of forming an antifuse on a semiconductor substrate using wet oxidation of a nitrided substrate
    Patent number: 7026217
    Abstract: A method of producing an antifuse includes introducing nitrogen by ion implantation means into the substrate. An oxide dielectric layer is then formed on the nitrided substrate in a wet oxidation ambient. The conditions of the ion implantation and the oxidation are controlled to generate a dielectric with uniform thickness and a low breakdown voltage when subjected to a high electric field.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: April 11, 2006
    Assignee: LSI Logic Corporation
    Inventors: Arvind Kamath, Venkatesh P. Gopinath, Wen-Chin Yeh, David Pachura
  • First time silicon and proto test cell notification
    Patent number: 7028276
    Abstract: A method for notification of a first new cell is disclosed. The method generally includes the steps of (A) generating a first report for a circuit design comprising a plurality of first cells including the first new cell by executing a rule check on the circuit design, (B) comparing the first report with a database comprising a plurality of second cells already manufactured and (C) notifying a client of the first new cell in response to the first new cell not matching any of the second cells.
    Type: Grant
    Filed: September 10, 2003
    Date of Patent: April 11, 2006
    Assignee: LSI Logic Corporation
    Inventors: Ekambaram Balaji, Cristian T. Crisan
  • Time multiplexing bus for DTV common interface
    Patent number: 7027526
    Abstract: A device for use in a digital video receiver. The device generally comprising a demodulator circuit, a decoder circuit, a plurality of bi-directional buffers, and a circuit. The demodulator circuit may be configured to generate (i) a first clock signal compliant with a standard interface for the digital video receiver and (ii) a first plurality of data signals compliant with the standard interface. The decoder circuit may be configured to receive a second plurality of data signals compliant with the standard interface. The plurality of first bi-directional buffers may be configured to multiplex the first data signals with the second data signals at a plurality of data interfaces in response to the first clock signal. The circuit may be configured to generate a direction signal at a direction interface in response to the first clock signal to indicate a direction of the data interfaces.
    Type: Grant
    Filed: March 1, 2002
    Date of Patent: April 11, 2006
    Assignee: LSI Logic Corporation
    Inventors: Yoed I. Nehoran, Yuanping Zhao
  • Input/output characterization chain for an integrated circuit
    Patent number: 7028238
    Abstract: An input/output characterization register is provided for characterizing an integrated circuit input or output. The register includes a normal data input, a characterization data input, and a data latch having a latch control input, a latch data input and a latch data output. The normal data input and the characterization data input are multiplexed with the latch data output to the latch data input.
    Type: Grant
    Filed: April 18, 2002
    Date of Patent: April 11, 2006
    Assignee: LSI Logic Corporation
    Inventors: Peter Korger, Brian Schoner
  • Base for a mogul-based lamp
    Patent number: 7025612
    Abstract: A lampsocket having a porcelain body that has a base, a peripheral wall, and at least two of a rigid, longitudinal spacer projecting axially outwardly from the base. The longitudinal upper surfaces of the spacers engage opposite areas of the bottom of the base of the lamp. The lampsocket is intended for use with and to operate a class of lamps having a threaded base having an insulated extension from the central portion of the bottom of the lamp base, and a central button mounted on the insulated extension. The lampsocket can also accept, but can not make electrical contact with, other lamps that have a conventional base contact without the insulated extension.
    Type: Grant
    Filed: March 18, 2005
    Date of Patent: April 11, 2006
    Assignee: LSI Industries, Inc.
    Inventors: Michael J. Keilholz, Mark C. Reed, Robert E. Kaeser
  • Real time binary arithmetic encoding
    Patent number: 7026961
    Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a plurality of signals in response to one or more of a context index and a binary symbol. The second circuit may be configured to generate a series of output bits in response to the plurality of signals. The memory may be configured to transfer the plurality of signals between the first circuit and the second circuit.
    Type: Grant
    Filed: May 3, 2004
    Date of Patent: April 11, 2006
    Assignee: LSI Logic Corporation
    Inventors: Eric Pearson, Michael D. Gallant, Harminder Banwait
  • Dynamic break loop for closed loop unmanaged stacking switches
    Patent number: 7027451
    Abstract: A dynamic break loop capable closed loop network having a plurality of switches and links. Each switch has two uplink ports that each have a set of dynamic break loop logic functions that may be enabled or disabled. The dynamic functions include inserting an ID number of a source switch into each frame that is transmitted from the switch, enabling a transmit function of each uplink port to monitor the ID number of each frame, and enabling a receive function of each uplink port to monitor the ID number of each frame. If the ID number is not equal to a filter ID number, then the frame will pass unchanged. If the ID number is equal to the filter ID number, then the frame will be cut off and will not be allowed to pass. The dynamic functions create a dynamic break for each switch in the network. The result is a closed loop network that operates dynamically as a plurality of open loop networks.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: April 11, 2006
    Assignee: LSI Logic Corporation
    Inventor: Mark Chiang