Abstract: A method of creating a layer-to-layer alignment mark in a semiconductor wafer includes the step of depositing a first conductor layer on a substrate associated with the semiconductor wafer. The method also includes the step of fabricating a number of alignment trenches in the first conductor layer. Moreover, the method includes the step of depositing a first insulator layer on the first conductor layer so as to fill the number of alignment trenches. Yet further, the method includes the step of removing material associated with the first insulator layer from the number of alignment trenches such that an upper surface of the first conductor layer and an upper surface of the first insulator layer define a first alignment step feature which possesses a predetermined height. The method also includes the step of depositing a second conductor layer on the semiconductor wafer subsequent to the removing step. A semiconductor wafer is also disclosed.

Abstract: A network interface unit which implements a low latency algorithm for buffer credit calculation. In one embodiment, a system network is provided with a remote node coupled to a local node by a serial communications link. The remote node is configured to transmit a data frame to the local node only if the remote node receives a buffer credit which indicates that the local node has available receive buffer space for a data frame. The local node includes a network interface unit for coupling to the serial communications link, and the network interface unit includes a receive buffer, a receive controller, a transmit controller, and a buffer credit manager. The receive controller stores incoming data frames in the receive buffer until they can be forwarded to the i/o bus of the local node. The transmit controller is configured to send buffer credits to the remote node in response to a credit signal from the buffer credit manager.

Abstract: A receive deserializer which regenerates parellel data words that have been broken into smaller data words and serially transmitted over multiple data channels uses an external state machine to shift word clocks with respect to data until the output of the channel last to receive a predefined data reference pattern is framed and provides storage to hold data for the channels which receive the reference pattern earlier.

Abstract: A method and apparatus for forming a dielectric layer. A dielectric precursor solution is deposited onto a surface of a substrate. The substrate is spun to spread the dielectric precursor solution over the surface of the substrate. A catalyst is introduced through a filter, wherein the filter causes a substantially homogenous distribution of the catalyst within the substrate, wherein a dielectric layer forms containing pores and wherein a solvent is contained in the pores. The solution is dried to form the dielectric layer using a carrier gas after introducing the catalyst, wherein the carrier gas places a positive pressure within the pores while removing the solvent to form a low-k dielectric layer.

Abstract: A circuit and method is provided which allows a microprocessor to implement speculative load instructions with implicit exception checking. In one embodiment of the method, exception information is generated in response to a memory access exception caused by a speculative load instruction for loading one of a plurality of first registers with data from memory. The exception information, once generated, is stored within one of a plurality of second registers. Each of the second registers corresponds to at least one of the plurality of first registers and is configured to store exception information. Thereafter, an instruction for operating on data stored in a first register is received and decoded by the microprocessor. In response, a second register corresponding to the first register is accessed. If this second register contains exception information, then the microprocessor initiates the exception routine.

Abstract: A method of fabricating an integrated circuit chip (IC), said method comprising the steps of defining the IC at the RTL code level, translating said RTL code into a generic netlist description, generating logic synthesis tool scripts based on said generic netlist description, and executing said logic synthesis tool scripts to synthesize the RTL code. The step of generating logic synthesis tool scripts comprises the substeps of identifying hardware elements and structure of the IC design, determining interrelationships between said identified hardware elements and structures, and generating logic synthesis tool scripts to synthesize said identified hardware elements to netlists as a function of said hardware elements and said interrelationships.

Abstract: A method of exposing an alignment mark defined in a first side of a semiconductor wafer includes the step of engaging a second side of the wafer with a wafer chuck. The method also includes the step of positioning the wafer in a chamber having a photochemical reactant gas present therein during the engaging step. Moreover, the method includes the step of impinging laser beams on the first side of the wafer such that a reactant specie is generated from the photochemical reactant gas. Yet further, the method includes the step of removing material from the first side of the wafer with the reactant specie. An apparatus for exposing an alignment mark defined in a first side of a semiconductor wafer is also disclosed.

Abstract: A single multifunctional structure can be used to determine the alignment accuracy of the contact layer and the interconnect layer by inline visual inspection and by determination of the end of line electrical resistance properties.

Abstract: A fuse circuit that includes a fuse and a full latch connected to the fuse. The fuse circuit is configured to receive a plurality of input signals including a preset signal and an enable signal. Preferably, a first pass gate is connected to the fuse and to the full latch and is configured to receive the enable signal and a second pass gate is connected to the full latch and is configured to receive the preset signal. Preferably, an output signal line is connected to the full latch and is configured to carry the output signal. The fuse circuit is configured to set the fuse using the preset signal. Ideally, the fuse circuit is configured to provide no direct path between VDD and VSS while using the preset signal to set the fuse. The fuse circuit is configured to provide an output signal which is dependent on the status of the fuse and the state of the enable signal.

Abstract: A method of determining circuit characteristics of an integrated circuit design as defined by a generic netlist comprising the steps of identifying hardware elements in the generic netlist, determining key characteristics for each of said identified hardware elements, determining interconnections of said identified hardware elements, and detecting the degree of conformity of said identified hardware elements, said key characteristics, and said interconnections to predetermined configurations. The systems further identifies all cells in the generic netlist, determines for each cell the type of cell, accumulates cell types and cell type counts, and notifies an operator of said accumulated values.

Abstract: A method for routing nets in an integrated circuit design, said method comprising the steps of forming a routing graph for an integrated circuit design, said routing graph have edges in a first direction and edges in a second direction, globally routing said integrated circuit design in accordance with said routing graph, dividing the routing graph into strips, for each strip in the routing graph, generating a general task for optimizing the routing in the strip, solving general tasks in parallel by assigning different processors different strips to process.

Abstract: A voltage controlled oscillator (VCO) having a generally linear transfer characteristic across a wide frequency range of operation. The VCO is comprised of a voltage-to-current converter (V-I) and a current-controlled oscillator (ICO). A linearization of the output response of the VCO is accomplished by proper selection of the output responses of the V-I and ICO circuits, where the V-I portion is designed to have an inverse nonlinearity response as compared to the nonlinearity response of the ICO portion of the VCO. The combined effect is a linear response for the VCO. A nonlinear V-I characteristic can be achieved by adding several piecewise linear responses together to produce a combined nonlinear response.

Abstract: A package for an integrated circuit is disclosed. The package comprises two layers (a top layer and a bottom layer) of flexible tape, each of which has a top surface and a bottom surface, with metal traces on the top surface. A die is mounted on top of the two layers and wire bonds connect bond pads on the die to metal traces on each of the two flexible tapes. The metal traces are routed along the top surfaces of the flexible tapes and are coupled to solder balls through holes in the tapes. These solder balls are mounted along the bottom of the package and serve as the electrical interface to a printed circuit board. Additional holes in the bottom layer tape allow solder balls to extend through the bottom layer tape so that they may be electrically coupled to traces on the top layer tape.

Abstract: A luminaire assembly includes a ballast housing, a wiring box mounted on an upper end of the ballast housing, and an optical assembly mounted on a lower end of the ballast housing. The ballast housing preferably includes a pair of identically configured ballast housing members that are integrally formed from sheet metal and folded by hand prior to final assembly of the ballast housing. The wiring box includes bent tabs that pivotally support the ballast housing between operative and inoperative positions to simplify installation of the luminaire assembly at a site. A hook and rotatable connector are provided to support the wiring box from a luminaire support member. An optional spacer box is provided to space the ballast housing from the wiring box as may be required in certain high wattage applications. The optical assembly is supported below the ballast housing by a pair of support arms that depend from the ballast housing and releasably engage with the optical assembly.

Abstract: An apparatus for polishing a first side of a semiconductor wafer down to a desired level includes a polishing platen having a polishing surface. The apparatus also includes a wafer carrier having a first sub-carrier and a second sub-carrier which is concentric to the first sub-carrier. The first sub-carrier is configured to engage a first radial portion of the wafer by a second side of the wafer and apply first pressure to the first radial portion in order to press the first radial portion against the polishing surface of the polishing platen. The second sub-carrier is configured to engage a second radial portion of the wafer by the second side of the wafer and apply second pressure to the second radial portion in order to press the second radial portion against the polishing surface of the polishing platen.

Abstract: A method and apparatus for automatically identifying the format of a sector in an optical storage device. Information on an optical disc is separated into data and subcode streams. The type of optical data is identified, and a first signal is generated to represent the type. Next, if the type is CD-ROM, the mode is identified, and a second signal is generated to represent the mode. Thirdly, if the mode is Mode-2 CD-ROM, the form is identified, and a third signal is generated to represent the form. A single signal may also be used to represent the type, mode, and form. In a CD embodiment, the type is identified by polling a type indicator bit, the mode is identified by polling the mode indicator bits, and the form is identified by comparing a first set of subheader bytes to a second set of subheader bytes, and polling a form indicator bit.

Abstract: The present invention relates to a semiconductor device, preferably a capacitor, and a method of forming the same. The method adds only a single additional masking step to the the fabrication process and reduces problems relating to alignment of various layers. A relatively thick insulation layer is formed over a bottom electrode. An opening having a sidewall that is etched in the insulation layer using a mask to expose a portion of the bottom electrode. Once the mask is removed, a dielectric layer and conductive layer are then sequentially deposited over the entire structure, including sidewalls. Thereafter, chemical-mechanical polishing is used to remove portions of the conductive layer and the dielectric layer so that the conductive layer and dielectric layer which remains forms, for example, the top electrode and dielectric layer of the integrated circuit capacitor.

Abstract: A network comprises at least one host processing system, a number of storage controllers, each coupled to one of a plurality of storage arrays, each storage array including at least one mass storage device. Each storage controller may be coupled to at least one host processing system and to at least one other storage controller to control access of the host processing systems to the mass storage devices. Multiple copies of data are maintained in storage arrays that are geographically remote to each other, such that any copy can be accessed by any host. Each storage controller includes an interface with a host that emulates a mass storage device and an interface with a local storage array that emulates a host. The interfaces to the host and local storage arrays are independent of the type of host or devices in the local storage array. Two or more hosts may be dissimilar to each other, and two or more storage arrays may include dissimilar mass storage devices. Hosts access stored data using virtual addressing.

Abstract: A method is disclosed for identifying regions of an integrated circuit layout design where optical proximity correction will be most useful and then performing optical proximity correction on those regions only. More specifically, the method includes the following steps: (a) analyzing an integrated circuit layout design with a design rule checker to locate features of the integrated circuit layout design meeting predefined criteria; and (b) performing optical proximity correction on the features meeting the criteria in order to generate a reticle design. The criteria employed by the design rule checker to select features include outside corners on patterns, inside corners on features, feature size, feature shape, and feature angles.

Abstract: A method and a circuit are described for generating a frequency signal having fine frequency control, and which are suitable for implementation on an-integrated circuit. The output frequency is generated having a controllable relationship with an oscillator frequency by using multiple phases of the oscillator signal. The output is provided by selecting a signal from the plurality of phases, and the frequency control is achieved by varying the selection cyclically, so that the output signal may be composed of segments of different phases. The cyclic selection is performed at a controllable rate to achieve stable generation of an original frequency signal.