Abstract: A packaging substrate includes a plurality of bonding pads and a plurality of gutters formed thereon. A die having conductive bumps on an electrically active surface thereof is positioned such that the conductive bumps of the die are electrically connected to the bonding pads of the packaging substrate. An underfill material fills the underfill space between the packaging substrate and the die to complete the structure. The plurality of gutters creates a linear flow front of the underfill material as it flows across the underfill space.

Abstract: A circuit isolation technique that uses implanted ions in embedded portions of a wafer substrate to lower the resistance of the substrate under circuits formed on the wafer or portions of circuits formed on the wafer to prevent the flow of injected currents across the substrate. The embedded ions provide low resistance regions that allow injected currents from a circuit to flow directly to a ground potential in the same circuit rather than flowing across the substrate to other circuits. High energy implantation processes on the order of 1 MeV to 3 MeVs can be used to implant the ions in embedded regions. Multiple energy levels can be used to provide thick embedded layers either prior to or after application of an epitaxial layer. Various masking materials can be used to mask the isolation regions during the implantation process, including hard masking materials such as silicon dioxide or silicon nitride, poly-silicon or an amorphous silicon layer, and a photoresist layer.

Abstract: A method for planarizing an integrated circuit. The integrated circuit is to be planarized to an upper surface using chemical mechanical polishing. The upper surface of the integrated circuit includes regions of a first material and regions of a second material. The first material has a first polishing rate and desired chemical, physical, and electrical properties. The second material has a second polishing rate and desired chemical, physical, and electrical properties. The first polishing rate is greater than the second polishing rate. The regions of the first material adjoin the regions of the second material at interfaces. The upper surface of the integrated circuit is overlaid with a top layer of the second material, that is to be removed by the chemical mechanical polishing. Both the regions of the second material and the top layer of the second material are deposited during a deposition.

Abstract: A recordable DVD disk which includes a read-only sector for specifying a video encoding algorithm to be used for compressing video programs that are to be recorded in the recordable region of the recordable DVD disk. Such disks may be used in a digital video recording system having a programmable video encoder. In one embodiment, the system accepts the recordable DVD disks having a read-only sector for storing customized video encoding algorithms and programs the programmable video encoder with the customized video encoding algorithms prior to encoding and recording a video signal on the disk. By designing the video encoding algorithms to optimize one or more of a number of desirable attributes, the DVD media vendors can then create “classes” of recordable DVD disks, i.e. high capacity, high quality, high speed, high image detail, high color resolution, variable frame rate, etc.

Abstract: A process is provided for removing resist mask material from a protective barrier layer formed over a layer of low k silicon oxide dielectric material of an integrated circuit structure without damaging the low k dielectric material, and without the necessity of subjecting the exposed via sidewalls of the low k dielectric material to either a pretreatment to inhibit subsequent damage to the low k dielectric material during the resist removal, or a post treatment to repair damage to the low k material after the resist removal. The resist removal process comprises exposing the resist mask material to a hydrogen plasma formed from a source of hydrogen such as ammonia, while maintaining the temperature below about 40° C. to inhibit attack of the low k silicon oxide dielectric material by oxygen released from the decomposition of the resist material.

Abstract: In order to correct for common phase error in demodulated digital video broadcast signals which comprise data modulated on a multiplicity of spaced carrier frequencies, a demodulator includes analog to digital conversion means (20) for providing a series of digital samples of the broadcast signal, real to complex conversion means (22) for converting each digital sample to a complex number value, Fourier Transform means (24) for analysing the complex number values to provide a series of data signal values in complex number format for each carrier frequency, and signal processing means for processing the series of data signal values including phase error correcting means (30), the phase error correcting means including means for converting the data signal values from a complex number format to a phase angle format, means for determining a common phase error by assessing the phase of continual pilot signals in the broadcast signals and determining the variation in phase of the continual pilot signals between c

Abstract: A method and apparatus utilizing a data processing system are disclosed for multi-level data communication providing self-clocking. A first digital signal is input which includes a series of digital bits. One of a plurality of output levels is associated with each group of data bits for each of the plurality of the digital bits included within the first digital signal. A particular output level is associated with a clock output level. An output signal is generate which includes a transmission of the output level for each of the groups of digital bits and includes multiple transmissions of the clock output level, where a clock output level is transmitted after each transmission of an output level for each of the groups of digital bits.

Abstract: A method of planarizing a semiconductor that includes (i) a substrate material, (ii) a first reflective substance positioned on the substrate material, (iii) an intermediate material positioned on the first reflective substance, wherein a channel is defined in a structure which includes the substrate, the first reflective substance, and the intermediate material, and (iv) a second reflective substance positioned on the intermediate material and in the channel is disclosed.

Abstract: High energy implantation through varying vertical thicknesses of one or more films is used to form a vertically modulated sub-collector, which simultaneously reduces both the vertical and lateral components of parasitic collector resistance in a vertically integrated bipolar device. The need for a sinker implant or other additional steps to reduce collector resistance is avoided. The necessary processing modifications may be readily integrated into conventional bipolar or BiCMOS process flows.

Abstract: A sample and hold in a switched capacitor circuit with frequency shaping. The sample and hold does not require a pair of large area, power-consuming operational amplifiers and, as such, consumes less power and less area. Preferably, the sample and hold is operable in four different states wherein a different set of switches are closed in each of the four states. The switches are controlled by two clock signals and a plurality of signals derived from the two clock signals, such as four signals derived from the two clock signals. Desirably, the sample and hold with frequency shaping is configured to sample a voltage across a first capacitor while a second capacitor is disconnected from said first capacitor, and is configured to thereafter connect the second capacitor to the first capacitor and possibly discharge at least a portion of a charge held in the first capacitor into the second capacitor.

Abstract: An address match determining device has an address filter memory (22) for storing a matrix or table having a plurality of elements each of which is a 1-bit address match determination data indicating whether or not a corresponding N-bit address code is available, and is distinguished by a pair of a first index composed of the m most significant or high-order m bits of the corresponding address code and a second index composed of the remaining lowest or low-order (N−m) bits of the corresponding address code. A received-address latch (21) extracts the high-order m bits and remaining low-order (N−m) bits from an address code latched thereinto.

Abstract: A system and method for partial erasure compensation for a read channel is disclosed. The method comprises receiving a signal at a first state, the first state having a branch extending to each of a plurality of possible next states, each branch corresponding to a target value, determining a partial erasure compensation for each of the target values corresponding to a branch between the first state and each of the possible next states based upon the first state and each of the possible next states, the partial erasure compensation being a function of an amplitude reduce by partial erasure, and modifying the target value with the determined partial erasure compensation.

Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60°. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.

Abstract: A support structure is provided between, preferably approximately midway between, a semiconductor die and the inner ends of the lead fingers of a lead frame. Intermediate portions of bond wires connecting the die to the lead fingers are bonded, or tacked, to an upper surface of the support structure. In this manner, the length of the bond wires can be doubled, and the lead fingers can be commensurately further from the die so that a greater number of lead fingers of a given size and spacing can be provided, while avoiding the problems associated with long bond wires.

Abstract: An ASIC device and method provide clock signals to load circuits having a balanced clock tree including a master clock line, for example a clock trunk or H-tree, and branched clock lines feeding the clock signals to load circuits and being balanced with respect to the delays and loads in domains of the ASIC device to which the branched clock lines supply the clock signals. The ASIC device and method generate derived clock signals by gating the master clock signal, in which the derived clock signals have a frequency reduced by a factor n>1 (n=2, . . . , N), which is adapted to the need of the load circuits in a particular domain, and route the master clock signal and/or the derived clock signal for a particular domain to the load circuit of said domain.

Abstract: When fade-in is detected at a time (&tgr;f), the remaining number of bits (R) is increased by Rup=G/2. Thus, the remaining number of bits R to be consumed in the GOP (n) becomes (3/2)G=(12/8)G. In this way, the remaining number of bits (R) is increased when fade-in is detected. This increases the bit rate in pictures coming after fade-in and requiring a large information content, thereby improving picture quality.

Abstract: A scripting tool for executing a script command having at least one parameter includes a display device, a processor, and a memory. The memory has stored therein instructions which when executed by the processor cause the processor to generate a user input control for a parameter of the script command based upon a definition file, and display the user input control upon the display device. The instructions of the memory when executed by the processor further cause the processor to receive user input via the user input control, and generate a parameter value based upon the user input. Moreover, the instructions when executed by the processor cause the processor to set the parameter of the script command equal to the parameter value, and execute the script command based upon the parameter.

Abstract: A method of using a frame sequence to transmit a data block from a transmitting device to a receiving device is disclosed. One step of the method includes generating a first frame of the frame sequence that includes a last portion of the data block and a relative offset which indicates a relative displacement between a first portion of the data block and the last portion of the data block. Another step of the method includes generating a second frame of the frame sequence that includes the first portion of the data block. The method also includes the step of transmitting the first frame of the frame sequence from the transmitting device to the receiving device before transmitting the second frame. Yet another step of the method includes receiving the first frame of the frame sequence from the transmitting device before receiving the second frame.

Abstract: A system and method for motion vector extraction and computation is embodied in an architecture adapted to overlap a data extraction process with a computation process and to provide 2-frame store decode with letterbox scaling capability, to extract a plurality of parameters usable for calculating a motion vector, and to compute motion vectors. The architecture is adapted to compute vertical and horizontal components of motion vectors in back-to-back cycles. The architecture includes a motion vector compute pipeline which, in a preferred embodiment includes a delta compute engine, a raw vector compute engine, a motion vector with respect to top left corner of picture block, or a combination of these logic circuits. The delta compute engine is adapted to generate a delta from a motion code and a motion residual and to compute a predicted motion vector in consideration of a motion vector of a previous macroblock.

Abstract: A system and method for fax transmission over a fax relay network that includes at least a wideband portion and a narrowband portion, includes a first fax relay gateway communicatively connecting a sending fax machine on the wideband portion of the network to the narrowband portion of the network, the first fax relay gateway receiving image data from the sending fax machine and outputting digitized image data in accordance with a data rate of the narrowband portion of the fax relay network. A second fax relay gateway, communicatively connects a receiving fax machine to the narrowband portion of the network. At least one of the first fax relay gateway or the second fax relay gateway includes a control process that determines whether an amount of data stored in a buffer in the fax relay gateway is greater or less than a particular threshold or determines that the amount of jitter in the narrow band network exceeds a particular threshold, and if so, initiates a retrain procedure to adjust the fax data rate.