Abstract: A bidirectional communications interface employs the same path for transmitting and receiving. The bidirectional communications interface includes one two winding transformer for both transmit and receive and an integrated circuit having a transmitter and a receiver each connected to the same pair of input/output pins. The interface enables a communications node in a communications network to transmit data to and receive data from other nodes in the network.

Abstract: A digital logic circuit, such as a FIFO memory includes pointers, or indicators, generated in two clock domains, between which information is transferred, to indicate a location in the digital logic circuit for transferring the information into or out of the digital logic circuit within either clock domain. Each pointer is encoded with a “2-hot” encoded value within one of the clock domains. The 2-hot encoded value of each pointer is sent to the other clock domain to synchronize the pointer to the other clock domain as well as to its original clock domain. Within each clock domain, the pointer generated therein and the pointer received from the other clock domain are used to determine whether the information can be transferred into or out of the digital logic circuit.

Abstract: Methods and systems for mapping logical disk addresses to physical locations so as to achieve consistent sustained performance for a striped disk array I/O subsystem. Stripes (regions) are defined by a region mapping table. Zones are defined by the disk manufacturer as groups of cylinders having identical number of sectors per track. Outer zones store more data and therefore provide a higher level of sustained performance as compared to inner zones. Substantially half the disks in the array are mapped such that logical sequential blocks are allocated from outer most, higher performance, zones to inner, lower performance, zones. The other half of the drives in the array are mapped from inner zones to outer zones. Each region (stripe) therefore includes a mix of higher performance zones and lower performance zones. Each region therefore provides more consistent sustained performance as compared to prior techniques.

Abstract: Provided is a technique for reducing skew in routing a clock signal in an integrated circuit device by prerouting an H trunk, dividing the H trunk into parts, and balancing delays in one of the parts by adding snaking wire. In a more particular aspect, the clock signal is prerouted as an H trunk, and the H trunk is divided into a left-top quadrant, a left-bottom quadrant, a right-top quadrant, and a right-bottom quadrant. The signal delays are balanced as between the two left quadrants by adding snaking wire, the signal delays are balanced between the two right quadrants by adding snaking wire, and the signal delays are balanced between the right half and the left half by adding snaking wire.

Abstract: A memory architecture which includes a plurality of memory cells arranged in rows and columns. A word line is connected to each row of memory cells, and a plurality of bit lines are connected to each column of memory cells. Providing that more than one bit line is connected to each column of memory cells improves the performance of large memories, provides reduced access times without having to increase the size of the memory, and provides that a large memory consumes less power. The bit lines may each be formed of the same material, or they may be formed of different material depending on the application. The memory cells may be disposed in a plurality of arrays, and the arrays may be symmetrical (i.e. where each array is the same size) or asymmetrical (i.e. where the arrays are not the same size).

Abstract: A method and apparatus for providing data backup in a computer system. Check information can be calculated and stored on a sequential arrangement of data drives such that the loss of a single data drive does not impair the reading or writing of information on that data drive. Should more than one data drive fail or several drives fail, data can still be resurrected by chaining back through the arrangement of drives to calculate lost information. An optimum number of drives can be determined when the known number of data drives and known number of check drives and known number of check drives associated with each data drive is known. Should a data drive fail, a system for re-establishing a new data drive out of the existing check drives can be implemented.

Abstract: A system and method to establish an end-to-end error correcting protocol between two voice band data modems over a network including voice band data relay gateways, where part of the end-to-end connection is via low data rate narrowband network. Using a partial implementation of V.42 LAPM protocol within the data relay gateways, the system allows the independent selection of modulation schemes at each gateway as well as increased user data throughput by removing non-informational data. Flow control of the user data to match the channel rate of the narrowband network may also be provided.

Abstract: A method and system are provided for real-time special effects processing, compressing and storing video signals. A memory is provided for storing plural frames including a sequence of one or more uncompressed frames. One or more processors are also provided for forming a sequence of special effect frames. Each special effect frame is a combination of one uncompressed frame (stored in the memory) and frame data other than the uncompressed frame (which combination can be a linear combination). The processor(s) also compresses the special effect frame.

Abstract: A method for routing nets in an integrated circuit design, said method comprising the steps of dividing the integrated circuit design with lines in a first direction and lines in a second direction, forming a routing graph having vertices and edges, wherein vertices correspond to locations where lines in the first direction cross lines in the second direction, routing nets as a function of said routing graph with parallel processors operating substantially simultaneously, determining the relative wire congestion among different areas in the integrated circuit design, and rerouting nets passing though areas with a relatively high wire congestion.

Abstract: An optical waveguide extends vertically within the interior of an IC-like structure to route optical signals between horizontal waveguides in different layers of horizontal optical interconnects. A light reflecting structure is positioned at the intersection of the horizontal and vertical waveguides to reflect the light. Multiple horizontal waveguides may join the vertical waveguide at a common intersection, to form a beam splitter or a beam combiner. Optical signals from one horizontal waveguide are diverted within the IC-like structure into another horizontal or vertical waveguide. The waveguide is formed with a light reflective structure at an intersection of the horizontal and vertical waveguides, and the waveguide is completed using damascene fabrication techniques.

Abstract: Provided is a technique for fabrication of a nitrided gate oxide and shallow trench isolation (STI) oxide liner in a semiconductor depletion into STI oxide and the RNCE in CMOS devices by introducing nitrogen to the STI edges of the p-well. This technique improves isolation performance and is also effective to harden the oxide to reduce boron penetration. Nitridization of the STI liner may be conducted on its own or in combination with gate oxide nitridization, both with beneficial effect with regard to the RNCE. The nitridization may also be focussed on the channel region of the gate oxide in particular in order to mitigate RSCE.

Abstract: The present invention includes a Command Queuing Engine (CQE) that is a firmware-assist block which processes some of the firmware tasks related to command and context management preferably for SCSI. When enabled, CQE will decode SCSI commands as they arrive, and determine if DMA contexts can be automatically configured and started to transfer the data for those commands. CQE can also program DMA contexts to automatically return status information either after the disk has completed a transfer (as in non-cached writes) or after the DMA transfer is completed (as in reads or cached writes). CQE also utilizes a buffer-based linked-list to queue the SCSI commands as they arrive for future DMA context configuration. The present invention provides automated recognition and linking of commands belonging to a common thread, i.e., are sequential. The present invention also provides extensive thread boundary information and flexible firmware control for reordering commands.

Abstract: A methodology for generating structural descriptions of complex digital devices from high-level descriptions and specifications is disclosed. The methodology uses a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is essentially a series of transformations operating upon various levels of design representations. At each level, the intended meaning (semantics) and formal software manipulations are captured to derive a more detailed level describing hardware meeting the design goals. Important features of the methodology are: capturing the users concepts, intent, specification, descriptions, constraints and trade-offs; architectural partitioning; what-if analysis at a high level; sizing estimation; timing estimation; architectural trade-off; conceptual design with implementation estimation; and timing closure.

Abstract: A flip-chip integrated circuit die includes a semiconductor substrate, electronic components implemented on the semiconductor substrate, several plural metal layers, wires routed between the electronic components on the metal layers, a top layer, and bump pads arranged in a hexagonal array on the top layer. According to another aspect, the invention is directed to flip-chip integrated circuit design, in which a circuit description is input and standardized cells which correspond to electronic components in the circuit description are obtained. The standardized cells are laid out on the surface of the die using a rectangular-based layout technique, and bump pads are laid out in a hexagonal array.

Abstract: A demodulator suitable for implementation in a single chip for demodulating digital video broadcast signals comprising data modulated on a multiplicity of spaced carrier frequencies, wherein an input broadcast signal is converted to a frequency sufficiently low to enable analog digital conversion of the signal, the demodulator comprising analog to digital conversion means (20) for converting the broadcast signal to a series of digital samples, real to complex conversion means (22) for converting each digital sample to a complex number value, Fourier transform means (24) for analyzing the complex number values to provide a series of signal values for each carrier frequency, frequency control means (9, 38), comprising means responsive to the output of said Fourier Transform means for producing a signal for controlling the frequency of the signal formed by said complex number values, and signal processing means for receiving the signal values and providing an output for decoding, the signal processing means incl

Abstract: Apparatus for arbitrating between requests from a plurality of sources for access to a shared resource, the apparatus comprising: a register means having a plurality of stages, each stage containing a designation of one of said sources, a plurality of stages containing a designation of the same source, logic means for accessing the register stages according to a priority scheme and for comparing the designation in each stage with requests for access, and granting access according to the match between the highest priority source designation and a memory request, and means for changing the contents of the register means subsequent to access grant.

Abstract: A recordable DVD disk which includes a read-only sector for specifying a video encoding algorithm to be used for compressing video programs that are to be recorded in the recordable region of the recordable DVD disk. Such disks may be used in a digital video recording system having a programmable video encoder. In one embodiment, the system accepts the recordable DVD disks having a read-only sector for storing customized video encoding algorithms and programs the programmable video encoder with the customized video encoding algorithms prior to encoding and recording a video signal on the disk. By designing the video encoding algorithms to optimize one or more of a number of desirable attributes, the DVD media vendors can then create “classes” of recordable DVD disks, i.e. high capacity, high quality, high speed, high image detail, high color resolution, variable frame rate, etc.

Abstract: A method of interfacing a third circuit with a first circuit that operates based upon a first clock signal and a second circuit that operates based upon a second clock signal includes the step of applying the first clock signal and the second clock signal to a clock selector for the third circuit. The method further includes the step of transferring first data signals between the third circuit and the first circuit at a first rate based upon the first clock signal. Another step of the method includes causing the clock selector to apply the first clock signal to the third circuit prior to the step of transferring the first data signals between the third circuit and the first circuit. Yet another step of the method includes transferring second data signals between the third circuit and the second circuit at a second rate based upon the second clock signal.

Abstract: Apparatus for demodulating digital video broadcast signals with an improved automatic frequency control comprises data modulated on a multiplicity of spaced carrier frequencies, including: analog to digital conversion device for providing a series of digital samples of the broadcast signal, Fourier Transform for analysing the samples to provide a series of data signal values for each carrier frequency signal processing devices for processing the series of data signal values including the phase-error-correcting, and automatic frequency control device for controlling the frequency of the signals input to the Fourier Transform Processor, wherein the automatic frequency control device includes coarse frequency control unit for controlling the frequency in terms of increments of the carrier spacing frequency, and fine frequency control unit for controlling the frequency for values less than a single carrier spacing frequency interval, wherein the coarse frequency unit includes recursive of filtering for assessing

Abstract: An initial phase control for an oscillator such as a differential ring voltage-controlled oscillator is disclosed. The initial phase control generally comprises a current source circuit coupled to a first node of the delay cell and a current provider. The current source circuit and current provider are preferably selectively and synchronously in an on or off state such that when the current source circuit and current provider are in an on state, the current source circuit draws a current through the first node of the delay cell and the current provider provides current through a second node of the delay cell. A method for controlling a delay cell and an initial phase control for a differential ring oscillator having a plurality of delay cells in a ring configuration are also disclosed.