Abstract: A method, system, and program for selectively testing output signals of an integrated circuit. The system comprising a mask generation file specifying output signals and test cycles and a verification module to check simulation output data and generate test pattern data. The verification module further comprising an extractor routine which receives the mask generation file and processes the simulation output data such that the test pattern data is coded to mask the specified output signals at the specified test cycles. The verification module further comprising margin analysis for determining if margin times of the coded test patterns fall below a minimum margin time setting.

Abstract: Provided is an apparatus and method for modifying the manufacture of chip carrier bond pads to increase the quality and reliability of semiconductor packages and ball joints in particular. This is accomplished by minimizing the corrosion of the barrier metal layer on the functional bond pads during gold deposition with the use of sacrificial pads electrically connected with the functional bond pads. According to one embodiment of the invention, a semiconductor package has copper conductive pads on a substrate that are exposed through a dielectric. Both functional and sacrificial (nonfunctional) copper conductive pads are provided. A barrier metal layer composed of nickel is electrolessly plated onto these conductive pads, and a bond metal layer of gold is deposited onto the nickel using electroless, generally immersion, gold plating.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a first output signal having a predetermined slew rate and propagation delay in response to a first input signal and a control signal. The second circuit may be configured to generate a second output signal having a predetermined slew rate and propagation delay in response to a second input signal and the control signal.

Abstract: A system and method upgrade an original data storage system into an enhanced data storage system. The original data storage system includes an original storage array controller device and an original storage array. The original data storage system is initially connected to a host system via a host bus and presents to the host system an original logical volume mapping associated with a logical identifier and mapped to a physical data set stored in individual storage devices in the original storage array. An enhanced storage array controller device is operatively connected to the host system via the host bus, and the original storage array controller device and a storage connection device coupled to another storage array are operatively connecting to the enhanced storage array controller device via an intermediate bus. The physical data set of the original storage array is redistributed across a plurality of storage arrays, including the original and the other storage arrays.

Abstract: Disclosed is an integrated circuit structure having one or more metal lines thereon with metal line sidewall retention structures formed on the sides of the metal lines. The metal line sidewall retention structures comprise a material sufficiently hard to inhibit lateral distortion or expansion of portions of the metal line during subsequent processing or use of the metal line. The metal line sidewall retention structures are formed by anisotropically etching a layer of a material sufficiently hard to inhibit lateral distortion or expansion of portions of the metal line after formation of a layer of such a material over and around the sides of the metal lines.

Abstract: The nonvolatile semiconductor memory device of the present invention includes: a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together; a channel region formed in the first surface region of the semiconductor substrate; a source region and a drain region which are formed in the surface of the semiconductor substrate so as to interpose the channel region therebetween; a first insulating film formed on the surface of the semiconductor substrate; a floating gate formed on the first insulating film; and a control gate which is capacitively coupled to the floating gate via a second insulating film. The first insulating film includes a first gate insulating film portion formed in the first surface region, and, a second gate insulating film portion formed in the step side region and the second surface region.

Abstract: A low dielectric constant multiple carbon-containing silicon oxide dielectric material for an integrated circuit structure is described which comprises a silicon oxide material including silicon atoms which are each bonded to a multiple carbon-containing group consisting of carbon atoms and primary hydrogens. Preferably such multiple carbon-containing groups have the general formula —(C)y(CH3)z, where y is an integer from 1 to 4 for a branched alkyl group and from 3 to 5 for a cyclic alkyl group, and z is 2y+1 for a branched alkyl group and 2y−1 for a cyclic alkyl group.

Abstract: A delay cell, a method for generating a delay, and a differential ring oscillator are disclosed. The delay cell provides a stable delay with a low voltage power supply, and has a high power supply rejection ratio. The delay cell generally comprises a first and second input receiver on a first and second branch, respectively, to receive an input to control a current on each branch, each branch includes an output node capacitively coupled to a power supply. Each branch may include a current source coupled between the output node and the power supply and/or a lower limit clamp coupled between the output node and the power supply to maintain an output at the output node above a lower limit. The delay cell may also include a first and a second current diverter coupled to the first and second branch for diverting current on the first and second branch away from the first and second input receiver, respectively.

Abstract: A method and apparatus for receiving packets from a bus. A packet is received at an interface to the bus. The packet is parsed, and a determination is made whether to retain the packet from the parsing of the packet. The packet is placed in a buffer with a header. The packet is moved from the buffer to another bus using information located within the header, wherein repeated parsing of the packet to move the packet to another bus is unnecessary.

Abstract: A method of fabricating a semiconductor wafer having an active area and an inactive outer clear out area includes the step of fabricating a number of active dies on a first side of the wafer such that each of the number of active dies is completely contained within the active area of the wafer. The method also includes the step of generating a laser beam with a laser device. Moreover, the method includes the step of scribing a code in the inactive outer clear out area of the wafer with the laser beam such that the code is completely contained within the inactive outer clear out area of the wafer. An apparatus for scribing a code in an inactive outer clear out area of a first side of a semiconductor wafer is also disclosed.

Abstract: A method and apparatus for performing efficient reseeks in an optical storage device. As data sectors are read by the optical storage device, address information corresponding to sectors being processed by the optical storage device is stored in a stack. The stack may be composed of shift registers that shift the address information of new sectors down the stack as they are read. When an interrupt occurs, a selector determines which stack location contains address information for the sector being processed, and transfers the address information to a register. The address information is held in the register until it is accessed by a microprocessor. The microprocessor uses the address information to determine a reseek location, and causes the sector being processed to be read again.

Abstract: A detection circuit for receiving a pair of unstable input signals along a pair of input leads and providing a stable output signal along an output lead, preferably to downstream circuitry. The detection circuit includes a plurality of transistors including a first transistor and a second transistor, wherein at least one of the first and second transistors is configured to turn on upon the detection circuit receiving input signals along the pair of input leads. At least one of the first and second transistors is configured to provide a signal along a lead to circuitry which is configured to condition the output signal and turn on a third transistor. The third transistor is connected to the first and said second transistors such that when the third transistor turns on, the third transistor prevents the first and second transistors from turning on until a new clock signal is received by the detection circuit.

Abstract: A method for planning the clock distribution network in the conceptual design phase of an ASIC device is provided herein that comprises partitioning the technology-independent description of the device into partitioned groups based on the clocking time of the clock recipients in each of the partitioned groups. In addition, a clock budgeting plan is generated by creating target timing groups and assigning each of the partitioned groups to one of the target timing groups based on the clocking time of the clock recipients in each of the partitioned groups. The clock recipients in each of the target timing groups clock at a substantially same time and clock recipients in different target groups clock at different times.

Abstract: A microprocessor is configured to fetch a compressed instruction set which comprises a subset of a corresponding non-compressed instruction set. The compressed instruction set is a variable length instruction set including 16-bit and 32-bit instructions. The 32-bit instructions are coded using an extend opcode, which indicates that the instruction being fetched is an extended (e.g. 32 bit) instruction. The compressed instruction set further includes multiple sets of register mappings from the compressed register fields to the decompressed register fields. Certain select instructions are assigned two opcode encodings, one for each of two mappings of the corresponding register fields. The compressed register field is directly copied into a portion of the decompressed register field while the remaining portion of the decompressed register field is created using a small number of logic gates.

Abstract: A host register interface testing system and method are disclosed. The system includes a host register unit including information that is indicative of a set of host registers corresponding to a programmable device under test. The system further includes a rule set unit including information that is indicative of constraints on values that the set of host registers may assume and a test setup generator configured to access the host register unit and the rule set unit and to generate a set of test setups based on the contents of the host register unit and the rule set unit where each test setup corresponds to a valid state of the set of host registers. In one embodiment, the test setup generator is suitable for applying a test setup from the set of test setups to the device under test. In one embodiment, the system may further include a verifier configured to receive the output of the device under test and, based thereon, for determining the functionality of the device under test.

Abstract: An integrated circuit output buffer includes a core terminal, a pad terminal, a pad pull-up transistor, a pad pull-down transistor, a pull-up voltage protection transistor, and a selectively conductive pad voltage feedback path. The pad pull-up transistor and the pad pull-down transistor are coupled to the pad terminal and are biased to respectively charge and discharge the pad terminal in response to a data signal received on the core terminal. The pull-up voltage protection transistor is coupled in series between the pad pull-up transistor and the pad terminal and has a control terminal and a well terminal. The selectively conductive pad voltage feedback path is coupled between the pad terminal and the well terminal of the pull-up voltage protection transistor.

Abstract: Accordingly, there is disclosed herein a fast word compare circuit suitable for use in a BIST or BISR environment. In one embodiment, the comparator includes a front end and a zero-detector circuit. The front end receives two or more words and compares them bitwise, generating a set of bit match signals that indicate which bits match. The zero detector receives the bit match signals from the front end and asserts an output signal when all the bit match signals indicate a match. The front end may consist of a set of exclusive-or (XOR) gates, each configured to generate a bit match signal from respective bits of the input words. The zero detector may include a set of bit transistors coupled in parallel between a first node and ground. Each bit transistor receives a respective bit match signal and conducts when the respective bit match signal is asserted.

Abstract: A square estimator computes an estimate of the square of an input number. The input number preferably is provided to combinational logic that logically manipulates the bits of the input number to generate an estimate of the square of the input number. The level of accuracy of the square generator can be programmed or predetermined by including or enabling various term generator logic units. Each term generator logic unit produces an output value that, when added to all of the other output values from the other term generators, provides an estimate of the square of the input number. Additionally, negative correction logic can also be incorporated into the square estimator for producing a negative correction value that when added to the estimate values from the various term generators, permits the square estimator to estimate the square of negative numbers as well as positive numbers.

Abstract: A data conversion circuit and method are disclosed for converting an N-bit data stream to an M-bit data stream. A FIFO memory device having multiple N-bit memory locations receives as an input consecutive N-bit sets of data and stores each consecutively received N-bit set of data in consecutive memory locations. A write pointer identifies a next available memory location at which the next N-bit set of data is to be stored. A first read pointer identifies a first memory location containing a first portion of a first M-bit set of data. A second read pointer identifies a second memory location containing a last portion of the first M-bit set of data. Provided as the first M-bit set of data are each of the N-bit memory locations between and including the memory location identified by the first read pointer and the memory location identified by the second read pointer.

Abstract: An inverse quantizer is provided with a reduced bit-width. In one embodiment, the inverse quantizer receives quantized DCT coefficients in sign+magnitude form with 1+11 bits of resolution, and produces reconstructed DCT coefficients with 1+11 bits of resolution. Although this is less than the theoretical minimum bit-width required to represent the entire reconstructed DCT coefficient range [−2048, 2047] mandated by the MPEG standard, certain IDCT implementations will maintain IEEE compliance when the −2048 value is replaced with −2047. (An example of one such implementation is provided in a co-pending application.) This reduces the range to [−2047, 2047]. In one embodiment, the inverse quantizer includes a dead-zone expander, a quantization multiplier, a mismatch controller, and a bit-width reducer. The dead-zone expander receives quantized coefficients with 1+11 bits of resolution, doubles them, and then increases their magnitude by one.