Abstract: A system and method for managing data stored in a cache block in a cache memory includes a cache block is located at a cache block address in the cache memory, and the data in the cache block corresponds to a storage location in a storage array identified by a storage location identifier. A storage processor accesses the cache block in the cache memory and provides a cache management command to a command processor. A processor memory coupled to the storage processor stores a search key based on the storage location identifier corresponding to the cache block. A command processor coupled to the storage processor receives a cache management command specified by the storage processor and transfers the storage location identifier from the processor memory. A cache management memory stores a cache management structure including the cache block address and the search key.

Abstract: A system for designing integrated circuits that use frequency synthesizers to ensure testability. A testability circuit is added or connected to the frequency synthesizer that will receive allow the integrated circuit to operate in a system mode for normal function and in a test mode during testing. In the test mode, the testability circuit will inhibit the reset signal from initializing the integrated circuit until the frequency synthesizer has reached phase lock. The testability circuit may be implemented as a component in the frequency synthesizer cell in an ASIC design system such that anytime the frequency synthesizer is used, the integrated circuit is testable.

Abstract: A method of fabricating contacts to device elements of an integrated circuit on a semiconductor substrate that includes: (a) using a plasma process to form a first hole in the material above a first portion of the device, wherein the first hole has a depth and a width at the end of the plasma process, and wherein the first hole has an aspect ratio at the end of the plasma process defined by its depth divided by its width; (b) using a plasma process to form a second hole in the material above a second portion of the device, adjacent to the first portion, wherein the second hole has a depth and a width at the end of the plasma process, and wherein the second hole has an aspect ratio at the end of the plasma process defined by its depth divided by its width; and (c) wherein the aspect ratio of the first hole is substantially equivalent to the aspect ratio of the second hole.

Abstract: Techniques are described for fabricating a pair of &bgr;-identical transistors, in other words, a pair of transistors whose dimensions and electrical characteristics, other than their respective gate electrode work functions, are substantially similar. In particular, the lengths of respective channel regions for the transistors are substantially the same, and portions of each gate electrode extending above a channel region include only dopants of a single conductivity type. The techniques can be incorporated into a standard CMOS process.

Abstract: An E-beam generator and detector arrangement sends an electron beam through a series of differentially evacuated vacuum chambers of small size to detect faulty circuitry in individual semiconductor devices. The vacuum chambers are open to one end and are sealed by the semiconductor device without contacting the vacuum chambers. A laser generator is operated by a control system with the E-beam generator and detector arrangement to provide a laser beam in a known physical relationship to the electron beam to correct detected faulty circuitry in the semiconductor devices. The E-beam generator and detector arrangement confirms the correction without further handling of the semiconductor device.

Abstract: A method is shown for manufacturing a semiconductor device in which a silicon oxide film acts as an insulating film for electrically isolating conductive layers included in the semiconductor device. An oxynitride silicon-oxide-like film is formed containing fluorine, carbon and nitrogen and having a given dielectric constant by CVD method using a source gas which contains at least silicon, nitrogen, carbon, oxygen and fluorine contributors. By controlling the ratio of nitrogen to oxygen in the source gas as used in the CVD method, the ultimate nitrogen, carbon and fluorine concentrations in the film can be controlled and hence the dielectric constant of the film so produced.

Abstract: A high order surface patch rendering system with adaptive tessellation. A patch is rendered by subdividing a patch until the subpatches are sufficiently flat that they can be approximated by a quadrilateral. To determine when a subpatch is flat enough to be approximated with a quadrilateral, the patch rendering system uses a patch flatness test unit which tests the straightness of the edges and internal curves of the subpatch. The edges and internal curves of a subpatch are determined to be straight if the intermediate control points of a curve are within a tolerance range of a straight line between the curve's endpoints. The tolerance range is chosen with respect to a pixel resolution of the final image so that subpatch is determined to be flat when the curvature of the subpatch cannot be perceived relative to a flat surface. One embodiment contemplates a flatness test unit for determining the flatness of a patch having a set of control points. The flatness test unit comprises a series of stages.

Abstract: A system and method identifies Iddq test vectors to be used in IDDQ testing of large CMOS circuits. This is achieved through intelligent preprocessing techniques. By monitoring only those nodes in the circuit that may be responsible for leakage current in the steady state, the size of the simulation results file is drastically reduced. The reduced simulation results file makes simulation a viable solution for IDDQ vector identification.

Abstract: A well wall of a second type of conduction is formed so as to surround a first IC formed in a first IC forming region specified by a region specifying means and to extend from a surface of a semiconductor substrate to a bottom well on the basis of information about the first IC forming region and information about the bottom well in a mask pattern produced by a bottom well mask pattern producing means.

Abstract: A system for emulating a mouse button event via an absolute coordinate input device. The system includes a computer having an operating system capable of receiving mouse type relative coordinate input commands from an absolute coordinate input device adapted to generate coordinate data in response to a finger touch down event. A controller is operably connected to the coordinate input device and adapted to resolve left and right mouse button touch down events and respective coordinate data for such events.

Abstract: The present invention provides bearing assemblies and methods of manufacturing bearing assemblies which allow for reliable, non-intrusive wear detection. In one embodiment, a bearing assembly (10) includes first and second bearing members (12, 14) adapted for movement relative to each other. The first bearing member includes an outer layer (24) that is adapted to wear in response to the relative movement between bearing members, and an inner layer. The inner layer includes a base portion (28) having a first hardness and a plurality of spaced apart wear indicating regions (30) having a second hardness, whereby the first hardness and second hardness are different. The wear indicating regions are adapted to produce a vibration after sufficient wear of the outer layer.

Abstract: An apparatus and method are presented for testing the ability of a pair of serial data transceivers to transmit serial data at one frequency and to receive serial data at another frequency. A serial communication device of the present invention includes a first and second serial data transceivers and a multiplexer formed upon a monolithic semiconductor substrate. Each serial data transceiver includes a receiver and a transmitter which transmits serial data in response to a clock signal. The second serial data transceiver is coupled to receive a reference clock signal. The multiplexer facilitates testing, and is coupled to the first serial data transceiver. The multiplexer receives the reference clock signal, a test clock signal, and a test signal, and provides either the reference clock signal or the test clock signal to the first transceiver dependent upon the test signal. The reference and test clock signals have different frequencies.

Abstract: A programmable multimedia accelerator which maximizes data bandwidth utilization with minimal hardware (and consequently minimal power consumption) is provided herein. In one embodiment, the accelerator includes four functional units, a routing unit, and a control module. The functional units each operate on four input bytes and a carry-in bit, and produce two output bytes and a carry-out bit. The carry-out bit of each functional unit is provided as a carry-in bit to another functional unit, allowing the functional units to operate cooperatively to carry out extended-precision operations when needed. The functional units can also operate individually to perform low-precision operations in parallel. The routing unit is coupled to the functional units to receive the output bytes and to provide a permutation of the output bytes as additional pairs of input bytes to the functional units.

Abstract: Provided is a method and composition for RF sputter cleaning of contact and via holes which provides substantially uniform charge distribution in the holes and minimizes electron shadowing. This is accomplished by isotropically depositing, such as by PVD, a layer of conductive material at the wafer surface surrounding a hole and down the sides of the hole. Isotropic deposition is such that in high aspect ratio trenches and holes deposition is heaviest at the top and minimal at the bottom (due to the deposition shadowing effect). The deposited conductive material is preferably a metal that is also used as a liner in the holes prior to depositing the plug material. The conductive material provides path for negative charge otherwise accumulating at the top of a hole during RF sputter cleaning to reach the bottom of the hole and thereby prevents accumulations of charge of one polarity in and around the hole. Thus, the stress on the gate oxide caused by conventional RF sputtering, described above, is relieved.

Abstract: A process is provided for removing etch residues from one or more openings formed in one or more layers of a low dielectric constant insulation material over a copper metal interconnect layer of an integrated circuit structure which includes cleaning exposed portions of the surface of the copper interconnect layer at the bottom of the one or more openings, the process comprising providing an anisotropic hydrogen plasma to cause a chemical reaction between ions in the plasma and the etch residues in the bottom of the one or more opening, including copper oxide on the exposed copper surface, to thereby clean the exposed portions of the copper surface, and to remove the etch residues without sputtering the copper at the bottom of the opening.

Abstract: A multiple-register-access-capable device includes a serial port coupled to a plurality of registers. The multiple-register-access-capable device is controlled by a state machine. Information in one of the registers identifies whether the device is in a single-register or multiple-register mode. The state machine which controls the device operates in a single-register mode if the bit is disabled and operates in a multiple-register mode if the bit is enabled. In single-register mode, the device operates in a manner known in the prior art whereby a single register is identified for reading or writing and data is then either written into the register or read out from the register in response to a write or read request. In multiple register mode, data is written into or read out from all registers in a selected group of registers in the device in response to the write or read request.

Abstract: A method of determining circuit characteristics of buffering tree nets of an integrated circuit (IC) design comprising the steps of determining source pins of the nets of the buffering tree, determining fanout of each of said source pins, determining active edges and active levels of each of said source pins, and presenting said source pins, said fanout, and said active edge on a report.

Abstract: A demodulator suitable for implementation in a single chip for demodulating digital video broadcast signals including data modulated on a multiplicity of spaced carrier frequencies, wherein an input broadcast signal is converted to a frequency sufficiently low to enable analog to digital conversion of the signal, converter for converting the broadcast signal to a series of digital samples in complex format, transformer for analyzing the digital sample values to provide a series of data symbol values for each carrier frequency and signal processor including channel equalizer for receiving the signal values and providing an output for decoding, automatic frequency controller for controlling the frequencies of the digital sampling signals applied to the transformer, and timing synchronizer for synchronizing the transformer with the symbol periods of the broadcast signal, including correlator for receiving the digital signal values and including a delay having a time period equal to the active symbol period, and

Abstract: An electronic device or flip chip includes a chip having an active side and an opposed side, with the active side electrically connected by bumps with the top of a substrate. A first material or underfill, generally located between the chip and the substrate, is resistive to electrical conductivity to isolate the flip chip bumps and their contacts. A second electrically conductive material is formed on a portion of the top of the substrate, the opposed side of the chip and over the first material to completely cover and protect the opposed side. The second material preferably has 80-95% metal fillers and is at least 75 microns (0.075 millimeters) thick. The second thermally/electrically conductive material transfers heat from the opposed or back side of the chip to provide a low cost flip chip package with comparable thermal performance to a flip chip with a heat spreader and a stiffener.

Abstract: An ATV receiver is provided with a 16-state trellis decoder to achieve improved performance in the presence of NTSC co-channel interference. In one embodiment, the ATV receiver comprises a tuner, a comb filter, and a trellis decoder. The tuner is configured to downmix a selected channel frequency signal to an intermediate frequency signal, where the comb filter is configurable to screen out most of the NTSC co-channel interference. The intermediate frequency receive signal is modified by the comb filter to resemble a partial response signal. The trellis decoder the demodulates the partial response signal in an improved fashion taking into account the state of the trellis encoder and the partial response channel. The trellis decoder may have a 16 state trellis comprised of four 4-state butterflies wherein each edge in the trellis is a single transition.