Abstract: An improved wafer scale integrated circuit is described which includes non-contact power and data transmission coupling. Wireless power and data coupling reduces the mechanical stresses and strains on the wafer, and makes better use of the wafer area. An additional benefit comes from allowing better heat transfer management. In one embodiment, power is provided by inductive coupling. Data flow into and out of the wafer is accomplished optically, using optical detectors to receive and light emitting diodes to transmit. Multiple devices are integrated onto the semiconductor wafer. Systems may be incorporated using the traditional die sites. Connections between systems are made in the space between die sites.

Abstract: An apparatus for etching a first side of a semiconductor wafer down to a desired level. The apparatus includes an etching chamber. The apparatus also includes a wafer chuck configured to engage the wafer by a second side of the wafer, and position the wafer in the etching chamber. The apparatus also includes a light source unit positioned such that light signals generated by the light source unit are directed into the wafer. Moreover, the apparatus includes a light receiving unit positioned such that the light signals generated by the light source unit emanate out of the wafer and are received with the light receiving unit. The light receiving unit includes a first optical material and a second optical material having an interface therebetween. The first optical material has a linear index of refraction, whereas the second optical material has a nonlinear index of refraction which is dependent on an intensity level of the light signals received with the light receiving unit.

Abstract: Apparatus, and an associated method, for performing error-correction operations to correct errors in a block of block-encoded data. Two ALUs are operable in parallel to perform finite-field mathematical operations and to calculate addresses used pursuant to the error-correction calculations. Instructions pursuant to which the ALUs are operable are stored in a memory device. The instructions are retrieved during operation of error-correcting calculations. The manner by which the error-correcting apparatus operates is alterable by appropriate alteration of the instructions stored at the memory device.

Abstract: The present invention is a method and apparatus for systematically applying proximity corrections to a mask pattern, wherein the pattern is divided into a grid of equally sized grid rectangles, an inner rectangle comprising a plurality of grid rectangles is formed, an outer rectangle comprising a second plurality of grid rectangles and the inner rectangle is formed and proximity correction is applied to the pattern contained within the inner rectangle as a function of the pattern contained within the outer rectangle.

Abstract: Routing of electrical connections between cells arranged in cell columns on an integrated circuit (IC) die. Electrical connections are routed on a routing layer between cells located in a first cell column. An identification is made of an available off-grid resource capable of being used for wire routing that is both within the first cell column and on the routing layer. An electrical connection is routed between a first cell and a second cell located in different cell columns using at least a portion of the identified available off-grid resource. Also, an integrated circuit die which includes vertical power rails and vertical ground rails. Cell columns, including a first cell column and a second cell column, are each bordered by a vertical power rail and a vertical ground rail. A channel is provided between the first cell column and the second cell column.

Abstract: A method of making a metal interconnect stack for an integrated circuit structure is described comprising a main metal interconnect layer, an underlying TiN barrier layer and a titanium metal seed layer below the TiN barrier layer, and a barrier layer below the titanium metal seed layer to provide protection against chemical interaction between the titanium metal seed layer and an underlying plug in a via. The structure is formed by providing an integrated circuit structure having an insulation layer formed thereon with one or more metal-filled vias or contact openings generally vertically formed therethrough to have an upper surface thereon; forming a lower barrier layer such as a TiN barrier layer over the insulation layer and the upper surface of the metal in the one or more metal-filled vias; and subsequently forming the titanium seed layer over the lower TiN barrier layer.

Abstract: Net routing is optimized in an integrated circuit device by dividing an integrated circuit design with a first group of substantially parallel lines in a first direction and with a group of substantially parallel lines in a second direction, with the second direction being substantially perpendicular to the first direction. A first routing graph is formed with vertices corresponding to locations where lines in the first direction and lines in the second direction cross, and nets are globally routed as a function of the first routing graph. The integrated circuit design is further subdivided with a second group of substantially parallel lines in the first direction, and a second routing graph is formed with vertices corresponding to locations where lines in the first and second groups of substantially parallel lines in the first direction cross lines in the group of substantially parallel lines in the second direction.

Abstract: The present invention is a method and apparatus for applying one-dimensional proximity correction to a piece of a mask pattern, by segmenting a first piece of a mask pattern with horizontal dividing lines into a plurality of segments, segmenting a second piece of said mask pattern with said horizontal dividing lines into a second plurality of segments, and applying proximity correction to a first segment from said first plurality of segments taking into consideration a second segment from said second plurality of segments.

Abstract: A method and apparatus for mirroring currents in application specific integrated circuits provides higher current mirroring accuracy than previously obtainable with matched active devices by using small groups of resistors with local matching to create a summing node which represents the average voltage across the source resistors of the active output devices and by forming a reference resistor through the combination of resistors from the local resistor groups such that the reference resistor has properties which will largely cause cancellation of location gradients and initial value variation in the resistor groups. An error amplifier compares the voltage at the summing junction with the voltage across the reference resistor and adjusts its output voltage to drive the paralleled gates of each active mirror output device such that the summing junction and reference resistor voltages remain equal.

Abstract: An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first control signal and a second control signal in response to (i) a digital input signal and (ii) a clock signal. The second circuit may be configured to generate a third control signal by scrambling the first control signal. The third circuit may be configured to generate a pulse width modulated output signal in response to (i) the second control signal and (ii) the third control signal.

Abstract: A gain control arrangement is suitable for controlling the gain of a variable gain amplifier in dependence on the difference between the actual magnitude and the desired magnitude of a read signal provided over an optical data carrier read channel. The amplitude of the read signal is sampled at periodic sampling points to determine an envelope value based on the sample value at a sampling point and an envelope value at a preceding sampling point, and a gain error value is derived from the difference between that envelope value and a desired envelope value.

Abstract: An apparatus and method for aligning any number of multiple parallel channels of data signals according to a single clock is provided. The synchronization process is accomplished through the use of a First-In-First-Out (FIFO) principle and individual storage elements implementing the FIFO principle for each received data channel. Each channel's data signals are read into a corresponding storage element, maintained in order, and read out upon the assertion of read signals in synchronization with a designated single clock signal. The apparatus and method preferably uses indications of data ready to be read from a storage element implementing the FIFO principle and the presence of a master clock signal to activate the reading of the data from the corresponding storage element. Therefore, each data channel is fully aligned with the master clock signal. The clock-data alignment function may be implemented for a 100BASE-T4 receiver.

Abstract: A method of synthesizing integrated circuit chip (IC) designs having clock signals defined internal to a module comprising the steps of mapping the IC design to a target technology with the internal clock defined, removing definitions of the internal clock, re-synthesizing the IC design, and re-defining the internal clock using new names of clock sources.

Abstract: The present invention retrieves data across independent computer nodes of a server cluster by providing for I/O shipping of block level requests to peer intelligent host-bus adapters (hereinafter referred to as HBA). This peer-to-peer distribution of block I/O requests is transparent to the host. The HBA has the intelligence to decide whether to satisfy a block I/O request locally or remotely. Each HBA driver utilizes the I2O protocol, which allows peer-to-peer communication independent of the operating system or hardware of the underlying network. In a first embodiment of the present invention, local and remote storage channels, within a node, are supported by a single HBA. In a second embodiment of the present invention, local storage channels, within a node, are supported by one HBA, and the remote storage channel, within a node, is supported by a separate HBA.

Abstract: An aerial image produced by a mask having transmissive portions is simulated by dividing the transmissive portions of the mask into primitive elements and obtaining a spatial frequency function corresponding to each of the primitive elements. The spatial frequency functions corresponding to the primitive elements are combined to obtain a transformed mask transmission function, and the transformed mask transmission function is utilized to generate a simulation of the aerial image.

Abstract: One or two, or more, additional conductive layers, separated from one another (if two or more) and separated from a patterned (signal) conductive layer are formed in a flexible substrate, for mounting a semiconductor die in a semiconductor device assembly. These additional layers are used as separate planes for carrying power and/or ground from outside the assembly to the die, on a separate plane from signals entering or exiting the die. TAB processes are disclosed for cutting, bending and bonding inner and outer portions of selected signal layer traces to respective inner and outer edge portions of the additional conductive layer(s), including a two-stage process of (1) first cutting, bending and tacking the selected traces to the additional layer(s), and then (2) repositioning a bonding tool and securely bonding the selected traces to the additional layer(s). A tool (die pedestal) for aiding in the assembly process is also disclosed.

Abstract: A retrofit luminaire assembly for mounting in an existing canopy fixture housing and methods of installing same. The retrofit luminaire assembly includes a planar panel having electrical control elements mounted to an upper surface of the panel. A lamp is received in a lamp socket mounted to the panel with a light-emitting section of the lamp extending away from a lower surface of the panel. A lens is mounted to the lower surface of the panel for enclosing the light-emitting section of the lamp. The panel preferably has a pair of oppositely directed pivot members which are adapted to engage with inwardly directed flanges of the canopy fixture housing to removably and pivotally support the panel for movement between a vertical, inoperative position and a horizontal, operative position. Methods of installing the retrofit luminaire assembly in the existing canopy fixture housing are also disclosed.

Abstract: A polishing pad for chemical-mechanical polishing of an integrated circuit surface is described. The polishing pad includes a first polishing area having a first value of a physical property; and a second polishing area having a second value of said physical property, which said second value is different from the first value, such that during chemical-mechanical polishing of an integrated circuit surface, the integrated circuit rotates and oscillates on the polishing pad so that a substantial portion of the integrated circuit surface contacts both the first and second polishing areas, wherein a width of said first and second polishing areas is greater than about 40 mils.

Abstract: The present invention includes a method of transferring data when some of the data is masked. A mask table is provided to a storage device where it is duplicated and stored with the duplicate. The duplicate data is compared to the original data for a data protection function. A mask index counter and mask bit counter maintain provide values for specific data that are to be processed. The counters are programmable so that if a transfer error occurs, counter values for the next data after the previously transferred good data is calculated and loaded therein. The present invention also has the capability not to transfer the last requested sector if that sector is masked. The present invention evaluates whether a stop count value equals a stop threshold value when a sector is identified as being masked. The stop count value is incremented for each sector that is read from the first storage device, regardless of whether that sector is to be transferred or masked.

Abstract: A system and method for a differential charge pump with reduced charge-coupling effects for use in integrated circuits such as a phase-lock loop are disclosed. The charge pump includes a first branch, a second branch, and a charge device. The first branch includes a first current source and sink coupled to a power supply and ground, respectively, a first current steering device coupled between the first current source and sink, and a first buffer coupled to the first current steering device between a first charge node and a first damp node. The second branch includes a second current source and sink coupled to a power supply and ground, respectively, a second current steering device coupled between the second current source and sink, and a second buffer coupled to the second current steering device between a second charge node and a second damp node.